gem5/arch
Gabe Black cf2f7e13bc Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

arch/sparc/isa/decoder.isa:
    Hand merged

--HG--
extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
2006-03-17 14:23:48 -05:00
..
alpha Merge m5.eecs.umich.edu:/bk/newmem 2006-03-16 14:08:31 -05:00
mips fix to LiveProcess (this change got deleted somehow) 2006-03-16 19:01:09 -05:00
sparc Merge m5.eecs.umich.edu:/bk/newmem 2006-03-17 14:23:48 -05:00
isa_parser.py Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
isa_specific.hh Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu 2006-03-14 18:28:51 -05:00
SConscript Moved registerfile.hh to regfile.hh 2006-03-14 16:05:44 -05:00