Added registerfile.hh and utility.hh
--HG-- extra : convert_revision : f825fcf53e716efc62e541692cb4ed26366abc26
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Gabe Black
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110
arch/alpha/registerfile.hh
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110
arch/alpha/registerfile.hh
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ALPHA_REGISTERFILE_HH__
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#define __ARCH_ALPHA_REGISTERFILE_HH__
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#include "arch/alpha/types.hh"
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#include "arch/alpha/constants.hh"
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#include "sim/faults.hh"
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class Checkpoint;
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namespace AlphaISA
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{
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typedef IntReg IntRegFile[NumIntRegs];
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typedef union {
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uint64_t q[NumFloatRegs]; // integer qword view
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double d[NumFloatRegs]; // double-precision floating point view
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} FloatRegFile;
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class MiscRegFile {
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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public:
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MiscReg readReg(int misc_reg);
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//These functions should be removed once the simplescalar cpu model
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//has been replaced.
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int getInstAsid();
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int getDataAsid();
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MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
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Fault setReg(int misc_reg, const MiscReg &val);
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Fault setRegWithEffect(int misc_reg, const MiscReg &val,
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ExecContext *xc);
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void copyMiscRegs(ExecContext *xc);
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#if FULL_SYSTEM
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protected:
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typedef uint64_t InternalProcReg;
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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private:
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InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
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Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
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void copyIprs(ExecContext *xc);
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#endif
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friend class RegFile;
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};
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struct RegFile {
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegs; // control register file
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Addr pc; // program counter
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Addr npc; // next-cycle program counter
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Addr nnpc;
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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inline int instAsid()
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{ return miscRegs.getInstAsid(); }
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inline int dataAsid()
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{ return miscRegs.getDataAsid(); }
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#endif // FULL_SYSTEM
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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} // namespace AlphaISA
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#endif
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156
arch/alpha/utility.hh
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156
arch/alpha/utility.hh
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ALPHA_UTILITY_HH__
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#define __ARCH_ALPHA_UTILITY_HH__
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#include "config/full_system.hh"
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#include "arch/alpha/types.hh"
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#include "arch/alpha/constants.hh"
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#include "arch/alpha/registerfile.hh"
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#include "base/misc.hh"
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namespace AlphaISA
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{
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static inline ExtMachInst
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makeExtMI(MachInst inst, const uint64_t &pc) {
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#if FULL_SYSTEM
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ExtMachInst ext_inst = inst;
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if (pc && 0x1)
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return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
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else
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return ext_inst;
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#else
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return ExtMachInst(inst);
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#endif
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}
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static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
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}
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static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 9 && reg <= 15);
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}
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static inline bool isCallerSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline Addr alignAddress(const Addr &addr,
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unsigned int nbytes) {
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return (addr & ~(nbytes - 1));
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}
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// Instruction address compression hooks
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static inline Addr realPCToFetchPC(const Addr &addr) {
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return addr;
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}
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static inline Addr fetchPCToRealPC(const Addr &addr) {
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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static inline size_t fetchInstSize() {
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return sizeof(MachInst);
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}
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static inline MachInst makeRegisterCopy(int dest, int src) {
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panic("makeRegisterCopy not implemented");
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return 0;
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}
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// Machine operations
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void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
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int regnum);
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void restoreMachineReg(RegFile ®s, const AnyReg ®,
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int regnum);
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param xc The execution context.
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*/
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template <class XC>
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void zeroRegisters(XC *xc);
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#if FULL_SYSTEM
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// Alpha IPR register accessors
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static inline bool PcPAL(Addr addr) { return addr & 0x1; }
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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static inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
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// User Virtual
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static inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
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// Kernel Direct Mapped
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extern inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
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static inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
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// Kernel Virtual
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static inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
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static inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(PageBytes - 1); }
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static inline Addr
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RoundPage(Addr addr)
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{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
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void initCPU(ExecContext *xc, int cpuId);
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void initIPRs(ExecContext *xc, int cpuId);
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/**
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* Function to check for and process any interrupts.
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* @param xc The execution context.
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*/
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template <class XC>
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void processInterrupts(XC *xc);
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#endif
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} // namespace AlphaISA
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#endif
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