Commit graph

967 commits

Author SHA1 Message Date
Gabe Black
5c546e3504 CPU: Only look up the nearest symbol in the kernel if you're actually in kernel code. 2009-02-25 10:22:36 -08:00
Gabe Black
9940e21fa9 CPU: Add a flag to identify a read barrier to the static inst class. 2009-02-25 10:19:33 -08:00
Gabe Black
da61c4b3ee CPU: Don't fetch when executing a macroop.
If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
2009-02-25 10:18:36 -08:00
Gabe Black
6ed47e9464 CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. 2009-02-25 10:16:15 -08:00
Gabe Black
5605079b1f ISA: Replace the translate functions in the TLBs with translateAtomic. 2009-02-25 10:15:44 -08:00
Gabe Black
a1aba01a02 CPU: Get rid of translate... functions from various interface classes. 2009-02-25 10:15:34 -08:00
Nathan Binkert
3fa9812e1d debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
Korey Sewell
6c5afe6346 Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context 2009-02-20 11:02:48 -05:00
Steve Reinhardt
89a7fb0393 Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
2009-02-16 08:56:40 -08:00
Nathan Binkert
f255957b90 style 2009-02-10 22:19:27 -08:00
Korey Sewell
cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Korey Sewell
973d8b8b13 InOrder: Import new inorder CPU model from MIPS.
This model currently only works in MIPS_SE mode, so it will take some effort
to clean it up and make it generally useful. Hopefully people are willing to
help make that happen!
2009-02-10 15:49:29 -08:00
Korey Sewell
34a5cd8870 ExeTrace: Allow subclasses of the tracer to define their own prefix to dump 2009-02-10 15:49:29 -08:00
Korey Sewell
2d0a66cbc1 CPU: Prepare CPU models for the new in-order CPU model.
Some new functions and forward declarations are necessary to make things work
2009-02-10 15:49:29 -08:00
Gabe Black
7b58511470 CPU: Don't always reset the micro pc on faults. Let the faults handle it. 2009-02-01 00:30:54 -08:00
Gabe Black
7720968949 X86: Make sure the predecoder is cleared out for interrupts. 2009-02-01 00:04:34 -08:00
Ali Saidi
35a85a4e86 Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). 2009-01-30 19:08:13 -05:00
Gabe Black
d9794784ba CPU: Add a setCPU function to the interrupt objects. 2009-01-25 20:29:03 -08:00
Nathan Binkert
f0fb3ac060 cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.
Make interrupts use the new wakeup method, and pull all of the interrupt
stuff into the cpu base class so that only the wakeup code needs to be updated.
I tried to make wakeup, wakeCPU, and the various other mechanisms for waking
and sleeping a little more sane, but I couldn't understand why the statistics
were changing the way they were.  Maybe we'll try again some day.
2009-01-24 07:27:21 -08:00
Nathan Binkert
10fc45da27 o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
Nathan Binkert
dbac448b08 thread_context: move getSystemPtr so SE mode can get to it.
There was really no reason that it should be FS only.
2009-01-19 20:36:49 -08:00
Nathan Binkert
8153790d00 SCons: centralize the Dir() workaround for newer versions of scons.
Scons bug id: 2006 M5 Bug id: 308
2009-01-13 14:17:50 -08:00
Richard Strong
81180a3bf0 This fix addresses an ill formed if statement that fails
to compile. The fix was the simple addition of another set
of parenthesis to ensure the correct condition resolution.
2009-01-11 22:45:03 -08:00
Gabe Black
b0ab5c894d Tracing: Make tracing aware of macro and micro ops. 2009-01-06 22:34:18 -08:00
Steve Reinhardt
1704ba2273 Make Alpha pseudo-insts available from SE mode. 2008-12-17 09:51:18 -08:00
Gabe Black
02cd18f536 SPARC: Truncate syscall args and return values appropriately. 2008-12-16 23:06:37 -08:00
Nathan Binkert
489e3e7381 eventq: use the flags data structure 2008-12-06 14:18:18 -08:00
Gabe Black
7a4d75bae3 CPU: Refactor read/write in the simple timing CPU. 2008-11-13 23:30:37 -08:00
Clint Smullen
1adfe5c7f3 O3CPU: Make the instcount debugging stuff per-cpu.
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
2008-11-10 11:51:18 -08:00
Nathan Binkert
9c49bc7b00 mem: update stuff for changes to Packet and Request 2008-11-10 11:51:17 -08:00
Gabe Black
846cb450f9 CPU: Make unaligned accesses work in the timing simple CPU. 2008-11-09 21:56:28 -08:00
Gabe Black
909380f3ee X86: Make the timing simple CPU handle variable length instructions. 2008-11-09 21:55:01 -08:00
Lisa Hsu
07969dbbf1 Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system.  To make them match,
here is a little change.
2008-11-05 15:30:49 -05:00
Lisa Hsu
dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
2008-11-04 11:35:42 -05:00
Lisa Hsu
d857faf073 Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
2008-11-02 21:57:07 -05:00
Lisa Hsu
67fda02dda Make it so that all thread contexts are registered with the System, even in
SE.  Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
2008-11-02 21:57:06 -05:00
Lisa Hsu
c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
2008-11-02 21:56:57 -05:00
Clint Smullen
95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU.
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
2008-10-27 18:18:04 -04:00
Lisa Hsu
8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
comments.
2008-10-23 16:49:17 -04:00
Nathan Binkert
9836d81c2b style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
Ali Saidi
b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-20 16:22:59 -04:00
Gabe Black
809f6cb6d1 CPU: Explain why some code is commented out. 2008-10-12 23:52:02 -07:00
Gabe Black
989fa4fc0f X86: Make the MicroPC type 16 bit. 2008-10-12 20:48:24 -07:00
Gabe Black
0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. 2008-10-12 19:32:06 -07:00
Gabe Black
f245358343 Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
Gabe Black
c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. 2008-10-12 16:59:55 -07:00
Gabe Black
2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
Gabe Black
d0a43ce2b2 X86: Fix the ordering of special physical address ranges. 2008-10-12 14:01:06 -07:00
Gabe Black
557bde43c3 X86: Make APICs communicate through the memory system. 2008-10-12 13:28:54 -07:00
Gabe Black
42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. 2008-10-12 11:08:00 -07:00
Gabe Black
d9f9c967fb Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
Gabe Black
c4f1cc3b48 CPU: Eliminate the get_vec function. 2008-10-12 08:24:09 -07:00
Gabe Black
0c3848732e CPU: Add a getInterruptController function 2008-10-11 16:13:58 -07:00
Gabe Black
f621b7b81f CPU: Eliminate the simPalCheck funciton. 2008-10-11 12:17:24 -07:00
Gabe Black
da7209ec93 CPU: Eliminate the hwrei function. 2008-10-11 02:27:21 -07:00
Nathan Binkert
94b08bed07 SimObjects: Clean up handling of C++ namespaces.
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
2008-10-09 22:19:39 -07:00
Nathan Binkert
e06321091d eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
2008-10-09 04:58:24 -07:00
Gabe Black
b66eb3b8d1 O3: Generaize the O3 IMPL class so it isn't split out by ISA.
--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
2008-10-09 00:10:02 -07:00
Gabe Black
f57c286d2c O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
2008-10-09 00:09:26 -07:00
Gabe Black
e09c403d32 O3: Generalize the O3 CPU object so it isn't split out by ISA. 2008-10-09 00:08:50 -07:00
Gabe Black
c5c6ad7ed6 CPU: Fix where setMicroPC was being called instead of setNextMicroPC. 2008-10-09 00:06:05 -07:00
Nathan Binkert
80d9be86e6 gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
2008-09-27 21:03:49 -07:00
Kevin Lim
b784903207 O3CPU: Fix thread writeback logic.
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
2008-09-26 07:44:07 -07:00
Kevin Lim
712a8ee700 O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls.
Just check CPU's nextPC before and after syscall and if it changes,
update this instruction's nextPC because the syscall must have changed
the nextPC.
2008-09-26 07:44:06 -07:00
Nathan Binkert
6efb930e19 gcc: Version 4.3 is pretty anal about shadowing types, placate it.
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
2008-09-22 08:25:57 -07:00
Ali Saidi
3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Gabe Black
3633a916c2 CPU: Get rid of two more duplicated CPU params. 2008-08-19 21:59:09 -07:00
Richard Strong
8d018aef0f Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
2008-08-18 10:50:58 -07:00
Nathan Binkert
ee62a0fec8 params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them.  While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
2008-08-11 12:22:16 -07:00
Nathan Binkert
50ef39af82 sockets: Add a function to disable all listening sockets.
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb.  Expose a function to disable those ports, and have the
regression scripts disable them.  There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
2008-08-03 18:19:55 -07:00
Steve Reinhardt
8e7ddce284 Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. 2008-07-15 14:38:51 -04:00
Ali Saidi
a4a7a09e96 Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
Ali Saidi
50e3e50e1a Make the cached virtPort have a thread context so it can do everything that a newly created one can. 2008-07-01 10:24:16 -04:00
Ali Saidi
9bd0bfe559 After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
2008-07-01 10:24:09 -04:00
Steve Reinhardt
caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Steve Reinhardt
6b45238316 Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
2008-06-21 01:04:43 -04:00
Nathan Binkert
67a33eed40 AtomicSimpleCPU: Separate data stalls from instruction stalls.
Separate simulation of icache stalls and dat stalls.
2008-06-18 10:15:21 -07:00
Nathan Binkert
163465ac08 ThreadState: Ensure that kernelStats is properly initialized 2008-06-17 21:11:20 -07:00
Nathan Binkert
e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Gabe Black
d093fcb079 CPU: Make the simple cpu trace data for loads/stores. 2008-06-12 00:35:50 -04:00
Ali Saidi
8af6dc118c SCons: add comments to SConscript documenting bug workaround
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
2008-04-10 15:38:10 -04:00
Ali Saidi
ed27c4c521 SCons: Manually specifying header only directories with Dir() works around the problem
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
2008-04-08 11:08:26 -04:00
Steve Reinhardt
93ab43288a Don't FastAlloc MSHRs since we don't allocate them on the fly.
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
2008-03-24 01:08:02 -04:00
Vilas Sridharan
21fd15ad9a O3CPU: Don't call dumpInsts if DEBUG is not defined
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
2008-03-06 00:27:09 -05:00
Korey Sewell
8fb74c238c Add comments in code to describe bug conditions.
This should help if somebody gets to the bug
fix before me (or someone else)...

--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
2008-02-27 17:50:29 -05:00
Korey Sewell
b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring
you are squashing from the current instruction # causing the thread exit.

--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
2008-02-27 16:53:08 -05:00
Korey Sewell
34715cc691 Fix offset in removeThread() function so that float registers start freeing up
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
2008-02-27 16:48:33 -05:00
Gabe Black
8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it.
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
2008-02-26 23:38:51 -05:00
Ali Saidi
9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults.
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
2008-02-14 16:14:35 -05:00
Steve Reinhardt
9d7a69c582 Fix #include lines for renamed cache files.
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
2008-02-10 14:45:25 -08:00
Stephen Hines
6cc1573923 Make the Event::description() a const function
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-02-06 16:32:40 -05:00
Stephen Hines
0ccf9a2c37 Add base ARM code to M5
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
2008-02-05 23:44:13 -05:00
Ke Meng
0b6876a0c0 The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state.
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
2008-01-14 11:47:32 -05:00
Steve Reinhardt
6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02 15:22:38 -08:00
Steve Reinhardt
cde5a79eab Additional comments and helper functions for PrintReq.
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
2008-01-02 13:46:22 -08:00
Steve Reinhardt
3952e41ab1 Add functional PrintReq command for memory-system debugging.
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2008-01-02 12:20:15 -08:00
Ali Saidi
45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something.
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-18 01:52:57 -05:00
Ali Saidi
71909a50de CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
2007-12-16 03:48:13 -05:00
Gabe Black
ab598eadbf imported patch pagewalker.patch
--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
2007-11-21 00:04:15 -08:00
Gabe Black
a12d5975cc Simple CPU fix simple mistake in translateDataWriteAddr.
--HG--
extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
2007-11-20 15:37:56 -08:00
Korey Sewell
d09ab2bd22 add thread id to misc. reg functions
--HG--
extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76
2007-11-15 20:35:49 -05:00
Korey Sewell
7c076479e4 add MicroPC functions back to thread context
--HG--
extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1
2007-11-15 20:35:31 -05:00
Korey Sewell
cf9dc4b151 add microPC stuff back in. got deleted on changeset propragation somehow.
--HG--
extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676
2007-11-15 19:48:53 -05:00
Korey Sewell
8f8e7fe08e put the flattenIndex stuff back in O3 AND put fatal() back in faults
--HG--
extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
2007-11-15 16:38:09 -05:00
Korey Sewell
641ee83e40 add core specific parameter to BaseCPU params
--HG--
extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
2007-11-15 14:18:56 -05:00
Korey Sewell
789153dff6 Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"
--HG--
extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
2007-11-15 03:10:41 -05:00
Korey Sewell
375ddf8d25 branch merge
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
2007-11-15 00:14:20 -05:00
Korey Sewell
2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-13 16:58:16 -05:00
Gabe Black
1048b548fa X86: Separate out the page table walker into it's own cc and hh.
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
2007-11-12 18:06:57 -08:00
Gabe Black
fce45baf17 X86: Work on the page table walker, TLB, and related faults.
--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
2007-11-12 14:38:31 -08:00
Gabe Black
f17f3d20be X86: Implement a page table walker.
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
2007-11-12 14:38:24 -08:00
Gabe Black
7a39457d7f X86: Make the micropc available through the thread context objects.
This is necssary for fault handlers that branch to non-zero micro PCs.

--HG--
extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264
2007-11-12 14:38:17 -08:00
Ali Saidi
422ab8bec0 TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.
--HG--
extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
2007-11-08 10:46:41 -05:00
Ali Saidi
cf1c25dbcc AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.
--HG--
extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
2007-11-08 10:46:41 -05:00
Ali Saidi
11b931df6a Interrupts: Inline some code and remove duplication.
--HG--
extra : convert_revision : 0631c601f281bdd2a12ff0d0ae94576780115c2a
2007-11-08 10:46:41 -05:00
Ali Saidi
e41197a3f8 CPU: Add function to explictly compare thread contexts after copying.
--HG--
extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
2007-11-08 10:46:41 -05:00
Gabe Black
19292d3f06 O3: Remove unneeded variable.
--HG--
extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
2007-11-06 12:51:08 -08:00
Steve Reinhardt
4b49bd47f4 String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).

--HG--
extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-10-31 18:04:22 -07:00
Ali Saidi
538fae951b Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-31 01:21:54 -04:00
Gabe Black
93da9eb7f6 CPU: Add functions to the "ExecContext"s that translate a given address.
--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
2007-10-22 14:30:45 -07:00
Ali Saidi
8351660273 CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.
--HG--
extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
2007-10-18 13:15:08 -04:00
Gabe Black
50e2d20cb8 Merge with head.
--HG--
extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
2007-10-02 23:03:38 -07:00
Gabe Black
a56c651980 Predecoder: Clear out predecoder state on an ITLB fault.
--HG--
extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
2007-10-02 22:21:38 -07:00
Gabe Black
7571e8346d CPU: Make the cpuid parameter get set in SE mode as well.
--HG--
extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
2007-10-02 18:33:57 -07:00
Gabe Black
988cdb49f2 CPU: Make the cpus check the pc event queues in SE mode.
--HG--
extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
2007-10-02 18:25:37 -07:00
Gabe Black
3eeda8008d CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well.
--HG--
extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
2007-10-02 18:22:36 -07:00
Ali Saidi
0acf891c32 CPU: fix sparc_fs booting with SimpleTimingCPU.
--HG--
extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
2007-10-01 02:55:27 -04:00
Ali Saidi
d2a4f595d6 Update stats for quiesced cycles
--HG--
extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
2007-09-28 13:22:14 -04:00
Ali Saidi
d325f49b70 Rename cycles() function to ticks()
--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-09-28 13:21:52 -04:00
Ali Saidi
887cd6a273 Update statistics to use cycles properly instead of ticks
--HG--
extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
2007-09-28 13:21:30 -04:00
Gabe Black
2dd65dc254 Merge with head.
--HG--
extra : convert_revision : f331b9cbd82086d63d4f35e18f9e08466c016225
2007-09-25 20:11:41 -07:00
Gabe Black
032a30f345 SPARC: Fix a stupid mistake which was breaking the SPARC regressions.
--HG--
extra : convert_revision : 34a11df0d467ea249211dd3aba86bc8d2aea45de
2007-09-25 20:00:46 -07:00
Gabe Black
418ddf43e6 X86: Get X86_FS to compile.
--HG--
extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
2007-09-24 17:39:56 -07:00
Gabe Black
f3f3747431 X86: Put in the foundation for x87 stack based fp registers.
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
2007-09-19 18:26:42 -07:00
Gabe Black
26044dca33 X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm.
--HG--
extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77
2007-09-04 23:39:57 -07:00
Gabe Black
941675690c X86: Get x86 to compile again after the simobject constructor change.
--HG--
extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
2007-08-31 13:02:58 -07:00
Miles Kaufmann
e4eea9ee04 Fix miscellaneous small typos.
--HG--
extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
2007-08-30 15:16:59 -04:00
Miles Kaufmann
54cc0053f0 params: Deprecate old-style constructors; update most SimObject constructors.
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-30 15:16:59 -04:00
Gabe Black
7227ab5f22 Merge with head
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26 21:45:40 -07:00
Gabe Black
80d51650c8 O3 CPU: Remove alignment check from dynamic instruction read/write functions.
--HG--
extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
2007-08-26 20:31:30 -07:00
Gabe Black
24bfda0fdf Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.
--HG--
extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
2007-08-26 20:29:09 -07:00
Gabe Black
e7e2d5ce90 Simple CPU: Added code that will split requests that cross block boundaries into multiple memory access.
--HG--
extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
2007-08-26 20:27:11 -07:00
Gabe Black
e056e49c45 Simple CPU: Make sure only instructions which complete without faulting are counted.
--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
2007-08-26 20:25:42 -07:00
Gabe Black
537239b278 Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-26 20:24:18 -07:00
Gabe Black
20e0a3792a Merge with head.
--HG--
extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
2007-08-21 16:19:46 -07:00
Kevin Lim
e1054170b5 o3: Fix for retry ID bug.
It should be cleared prior to the call to recvRetry.
Add extra DPRINTF statement for clearer debugging output.

--HG--
extra : convert_revision : e2332754743f42d60e159ac89f6fb0fd8b7f57f8
2007-08-21 16:16:56 -07:00
Gabe Black
92a57edff1 O3: Set up the predicted npc and nnpc for a fault carrying noop so that it doesn't cause a false branch mispredict.
--HG--
extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
2007-08-13 16:08:58 -07:00
Gabe Black
82f78ebd39 Move the "translate" member functions back into the base o3 class.
--HG--
extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
2007-08-13 16:01:09 -07:00
Vincentius Robby
ec4000e0e2 Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.

--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-08 18:43:12 -04:00
Vincentius Robby
3d40cba8d4 Port, StaticInst: Revert unnecessary changes.
--HG--
extra : convert_revision : e6ef262bbbc5ad53498e55caac1897e6cc2a61e6
2007-08-08 14:54:02 -04:00
Vincentius Robby
13d10e844c alpha: Make the TLB cache to actually work.
Improve MRU checking for StaticInst, Bus, TLB

--HG--
extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
2007-08-08 14:18:09 -04:00
Gabe Black
0fd999ca40 Merge with head.
--HG--
extra : convert_revision : ae7b3df573368c29a66d5b027ecad9ffb3a99104
2007-08-07 15:31:36 -07:00
Gabe Black
fb6cdf09cb X86: Make a microcode branch microop.
Also some touch up for ruflag.

--HG--
extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
2007-08-07 15:19:26 -07:00
Nathan Binkert
df015f17a4 switching: turn on profiling after a switch if there's an event
--HG--
extra : convert_revision : 689e5b85c47bb2aaceb7eb38c2a24a2e5b69376c
2007-08-04 16:11:11 -07:00
Nathan Binkert
e8e1ddd530 SimpleCPU: Add some DPRINTFs
--HG--
extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
2007-08-04 15:56:48 -07:00
Vincentius Robby
acac5580f2 StaticInst: Fix decode cache initialization. Cache functionality was negated.
--HG--
extra : convert_revision : fe313718dba8236f3e9bceb49f8c5efccfc06a06
2007-08-04 14:25:17 -04:00
Gabe Black
8da3e0548e Merge with head.
--HG--
extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
2007-08-01 15:12:07 -07:00
Gabe Black
e42524af02 X86: Reorganize the native tracing code.
Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat.

--HG--
extra : convert_revision : 2c1f69d4e55b443e68bfc7b43e8387b02cf0b6b5
2007-08-01 12:01:51 -07:00
Gabe Black
4bdabe1254 Add a flag to indicate an instruction triggers a syscall in SE mode.
--HG--
extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
2007-07-31 17:34:08 -07:00
Steve Reinhardt
c4c8a12186 Merge from head.
--HG--
extra : convert_revision : af16bc685ea28e44b8120f16b72f60a21d68c1e2
2007-07-31 00:37:07 -04:00
Gabe Black
24ac08daa4 Fix problem with tracer not being initialized.
--HG--
extra : convert_revision : 09610ad84afa605db2d0eab9945eb9809f297182
2007-07-30 13:13:11 -07:00
Steve Reinhardt
08474ccf68 Merge Gabe's changes from head.
--HG--
extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
2007-07-29 13:25:14 -07:00
Steve Reinhardt
362ff1bceb BsaeCPU: Get rid of some bad DPRINTFs.
People should never put pointers in DPRINTFs; it messes up
tracediffs.  Plus these used the FullCPU trace flag, which
is not right.

--HG--
extra : convert_revision : 82ed56757da0ad947c165ba205b5f752c85c6667
2007-07-29 13:22:44 -07:00
Gabe Black
b6395da4ce X86: Fix register ordering.
The correct order is unintuitively rax, rcx, rdx, rbx, etc, not rax, rbx, rcx, rdx.

--HG--
extra : convert_revision : 3abe6a723a6e30becfe34f8da707ea2ff5d4df77
2007-07-29 01:28:36 -07:00
Gabe Black
8dd7700482 Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.

--HG--
extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-28 20:30:43 -07:00
Steve Reinhardt
aaf59949e5 AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.
--HG--
extra : convert_revision : 367bf2431bf4f4eb7c4d5723816e5db6f7233aed
2007-07-28 18:00:05 -07:00
Steve Reinhardt
0cbcb715e0 cache/memtest: fixes for functional accesses.
--HG--
extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
2007-07-27 12:46:45 -07:00
Nathan Binkert
f0fef8f850 Merge python and x86 changes with cache branch
--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26 23:15:49 -07:00
Gabe Black
d1e533a1e2 X86: Fix argument register indexing.
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.

--HG--
extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
2007-07-26 22:13:14 -07:00
Nathan Binkert
abc76f20cb Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-23 21:51:38 -07:00
Steve Reinhardt
97f7ee2e50 Fix WriteReq/StoreCondReq setting in O3.
--HG--
extra : convert_revision : b41571535f3d1f78df3cb6e48c16de5c7549d87f
2007-07-23 08:18:51 -07:00
Steve Reinhardt
f67c8b33cc Fix bug with timing snoop upcalls to MemTest object.
--HG--
extra : convert_revision : 1940a5d231b4f856cf69578f68ea98435824dbd8
2007-07-15 21:03:12 -07:00
Steve Reinhardt
884807a68a Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work.  Timing is closer but not there yet.

--HG--
extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15 20:11:06 -07:00
Steve Reinhardt
9172876dd7 Fix problem with unset max_loads in memtest.
Also make default 0, and make that mean run forever.

--HG--
extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
2007-07-15 14:32:55 -07:00
Steve Reinhardt
4b68652c87 Couple more minor bug fixes for FS timing mode.
src/cpu/simple/timing.cc:
    Fix another SC problem.
src/mem/cache/cache_impl.hh:
    Forgot to call makeTimingResponse() on uncached timing responses.

--HG--
extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
2007-07-02 13:57:45 -07:00
Steve Reinhardt
e9c04dad60 Fix a couple LL/SC bugs that only affected timing mode.
src/cpu/simple/timing.cc:
    Fix swap/stq_c command bug.
src/mem/packet.cc:
    Fix incorrect LoadLockedReq command response field.

--HG--
extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
2007-07-02 09:26:36 -07:00
Steve Reinhardt
3ad761bc8e Make CPU models use new LoadLockedReq/StoreCondReq commands.
--HG--
extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
2007-06-30 20:35:42 -07:00
Steve Reinhardt
ee54ad318a Event descriptions should not end in "event"
(they function as adjectives not nouns)

--HG--
extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
2007-06-30 17:45:58 -07:00
Steve Reinhardt
6ab53415ef Get rid of Packet result field. Error responses are
now encoded in cmd field.

--HG--
extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-30 10:16:18 -07:00
Steve Reinhardt
7f3dfa7c09 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : b1c954c187e3b3172a194396ba63808253121195
2007-06-28 08:28:58 -07:00
Korey Sewell
e28cbc98a0 o3cpu build for mips
--HG--
extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452
2007-06-28 05:30:46 -04:00
Steve Reinhardt
245b0bd9b9 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

src/base/traceflags.py:
    Hand merge.

--HG--
extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
2007-06-23 13:26:30 -07:00
Steve Reinhardt
57ff2604e5 Minor fix plus new assertion to catch similar bugs.
src/cpu/memtest/memtest.cc:
    Need to set packet source field so that response from cache
    doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
    Copy source field when copying packets.
    Assert that source is valid before copying it to dest
    when turning packets around.

--HG--
extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
2007-06-23 13:24:33 -07:00
Steve Reinhardt
ed1db23b41 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
2007-06-22 16:13:53 -07:00
Korey Sewell
753adb38d5 mips import pt. 1
src/arch/mips/SConscript:
    "mips import pt.1".

--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
2007-06-22 19:03:42 -04:00
Gabe Black
49490b334a Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro

src/cpu/o3/fetch_impl.hh:
    hand merge

--HG--
extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
2007-06-21 20:35:25 +00:00
Steve Reinhardt
eff122797b Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
2007-06-21 12:03:22 -07:00
Steve Reinhardt
83af0fdcf5 Getting closer...
configs/example/memtest.py:
    Add progress interval option.
src/base/traceflags.py:
    Add MemTest flag.
src/cpu/memtest/memtest.cc:
    Clean up tracing.
src/cpu/memtest/memtest.hh:
    Get rid of unused code.

--HG--
extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21 11:59:17 -07:00
Gabe Black
df7730b677 Fix compiler errors.
--HG--
extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
2007-06-20 19:46:45 -07:00
Vincentius Robby
d540dde5b4 Removed "adding instead of dividing" trick.
Caused slowdown in performance instead of speeding up.

src/cpu/base.cc:
    Removed "adding instead of dividing" trick.
src/mem/bus.cc:
    Fixed spelling in comments.
    Removed "adding instead of dividing" trick.

--HG--
extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488
2007-06-20 14:54:17 -04:00
Nathan Binkert
f65e2710ec Don't do checker stuff if the checker is not defined
--HG--
extra : convert_revision : 1c920b050c21e592a386410e4e9f45354f8e4441
2007-06-20 08:15:06 -07:00
Nathan Binkert
b47737dde7 Make sure all parameters have default values if they're
supposed to and make sure parameters have the right type.
Also make sure that any object that should be an intermediate
type has the right options set.

--HG--
extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
2007-06-20 08:14:11 -07:00
Gabe Black
5c48a05813 Merge zizzer.eecs.umich.edu:/bk/newmem
into  doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro

src/cpu/base_dyn_inst_impl.hh:
src/cpu/o3/fetch_impl.hh:
    Hand merge

--HG--
extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d
2007-06-19 18:54:40 -07:00
Gabe Black
cc796de962 Missed an "offset" to get rid of.
--HG--
extra : convert_revision : 7542f130b269a6a09e6ed51ae4689d1faa45a155
2007-06-19 19:01:02 +00:00
Gabe Black
ea70e6d6da Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
--HG--
extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
2007-06-19 18:17:34 +00:00
Ali Saidi
2d08ab0cc2 fix bug in timing cpu. getTime() is the time the requset was created, not the time it was repsonded to. In timing mode the
time it was responded to is curTick. Doesn't change the results, but it does make implementation of nextCycle() more difficult

--HG--
extra : convert_revision : 67ed6261a5451d17d96d5df45992590acc353afc
2007-06-18 18:11:07 -04:00
Steve Reinhardt
d69a763833 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

configs/example/memtest.py:
    Hand merge redundant changes.

--HG--
extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17 17:30:24 -07:00
Steve Reinhardt
35cf19d441 More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
    Revamp options.
src/cpu/memtest/memtest.cc:
    No need for memory initialization.
    No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
    MemTest really doesn't want to snoop.
src/mem/bridge.cc:
    checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
    More major reorg.  Seems to work for atomic mode now,
    timing mode still broken.

--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-17 17:27:53 -07:00
Steve Reinhardt
f4babe1082 memtest.cc:
No need to initialize memory contents; should come up as 0.

src/cpu/memtest/memtest.cc:
    No need to initialize memory contents; should come up as 0.

--HG--
extra : convert_revision : 1713676956f3d33b4686fee2650bd17027bcc495
2007-06-16 14:05:05 -07:00
Vincentius Robby
5b5570e0bf Modified instruction decode method.
Make code compatible with new decode method.

src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
    Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
    Modified instruction decode method.

--HG--
extra : convert_revision : a9a6d3a16fff59bc95d0606ea344bd57e71b8d0a
2007-06-14 16:52:19 -04:00
Gabe Black
6641423a0b A fix for SPARC_FS compilation.
--HG--
extra : convert_revision : 8af0dd9c16e7db8ed92f7a71c396841d5ae7e072
2007-06-14 13:27:08 +00:00
Gabe Black
cd8f604cc9 Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst.
src/arch/x86/predecoder.cc:
    Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.

--HG--
extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
2007-06-13 20:09:03 +00:00
Gabe Black
02732929e8 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 1d2efac895a1c8328026a079e0b319a436325616
2007-06-12 17:19:14 +00:00
Gabe Black
a7f3bbcfab Make microOp vs microop and macroOp vs macroop capitilization consistent.
src/arch/x86/isa/macroop.isa:
    Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
    Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.

--HG--
extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
2007-06-12 16:21:47 +00:00
Nathan Binkert
125237d357 Rename enum from OpType to OpClass so it's consistent with the
real thing.  Also rename the null case to something that can
be a C++ symbol.

--HG--
extra : convert_revision : e3bfc4065b59c21f613e486d234711c48d7c9070
2007-06-11 23:10:58 -07:00
Nathan Binkert
11f1c8dd3e Use the right type
--HG--
extra : convert_revision : b5ca3153ca786ea4e86bfe83f7760ba9ee41a882
2007-06-09 23:00:13 -07:00
Ali Saidi
42174babbb don't be so aggressive with the tracing on #if
--HG--
extra : convert_revision : 8ee88bff8010dcb7a412f6a6b49d40fad1c0bb68
2007-06-04 15:53:04 -04:00
Gabe Black
e47f1667b6 Don't mask the pc because the Alpha predecoder needs it to set the PAL mode bit in the ExtMachInst.
--HG--
extra : convert_revision : 87dc6e6b2281b6a11a0c0e8320b7f4acc29f6fb8
2007-06-02 03:41:47 +00:00
Nathan Binkert
aba2eeaf8f Fix typo so m5.fast will compile
--HG--
extra : convert_revision : 8ceb816c17108d7cb65cb46d8dc2bd2753b0e0f0
2007-06-01 20:41:46 -07:00
Ali Saidi
d8f6769962 cast sizeof(MachInst) to Addr before generating a mask
--HG--
extra : convert_revision : 1ae34a069bbd997a8f888f69415fbeaaf4ade0b3
2007-06-01 14:16:58 -04:00
Ali Saidi
d8c487c401 don't generate trace data unless tracing is on
--HG--
extra : convert_revision : 3953ace8d481d758d6e0d89183c0a7e7bebcf681
2007-06-01 13:44:24 -04:00
Gabe Black
c432588981 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/cpu/simple/base.cc:
    Hand merge

--HG--
extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d
2007-05-31 20:45:04 +00:00
Vincentius Robby
83aa742d26 Merge zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/.automount/greenville/w/acolyte/newmem

--HG--
extra : convert_revision : c80b7ef5a2cc4ab1b86bb1eef7fae91886a7737d
2007-05-31 16:02:31 -04:00
Vincentius Robby
ecf1eb7248 Assign traceData to be NULL at BaseSimpleCPU constructor.
Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
exec tracing isn't needed for m5.fast binaries
Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.

src/arch/sparc/miscregfile.cc:
    Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead.
src/cpu/simple/base.cc:
    Assign traceData to be NULL at BaseSimpleCPU constructor.
    Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls.
    exec tracing isn't needed for m5.fast binaries

--HG--
extra : convert_revision : 5dc92fff05c9bde994f1e0f1bb40e11c44eb72c6
2007-05-31 16:01:41 -04:00
Nathan Binkert
7797a239cc Fix cut-n-pasto to make the path correct
--HG--
extra : convert_revision : a6194cc9c3b2eb83dc8480ed0417b2246f07b4bd
2007-05-30 17:19:20 -07:00
Steve Reinhardt
05915ed6f7 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 6f462916cb0eb309b6799e94fbf07629abb50eba
2007-05-28 08:13:40 -07:00
Steve Reinhardt
07bda077f2 Remove unnecessary include of physical.hh.
--HG--
extra : convert_revision : bccafe884e58a55b02ff408448e6644196e439a4
2007-05-28 08:03:13 -07:00
Steve Reinhardt
075f4b108a Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79
2007-05-27 21:34:37 -07:00
Nathan Binkert
35147170f9 Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-27 19:21:17 -07:00
Gabe Black
a3ae9486d5 Merge zizzer.eecs.umich.edu:/bk/newmem
into  doughnut.mwconnections.com:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 276d00a73b1834d5262129c3f7e0f7fae18e23bc
2007-05-25 19:29:32 -07:00
Steve Reinhardt
0484867d85 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

src/mem/cache/base_cache.hh:
    Manual conflict resolution.

--HG--
extra : convert_revision : 5ebfd7abb4f978caa88bf43d25935869edfc6b9f
2007-05-22 06:36:01 -07:00
Steve Reinhardt
41dde5f6fd memtest.hh:
Fix description string.
Minor whitespace cleanup.

src/cpu/memtest/memtest.hh:
    Fix description string.
    Minor whitespace cleanup.

--HG--
extra : convert_revision : 0c7213d088da46de9713ca6beabc30523ccb1c8c
2007-05-22 06:32:24 -07:00
Steve Reinhardt
41241799ae Change getDeviceAddressRanges to use bool for snoop arg.
--HG--
extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-21 23:36:09 -07:00
Steve Reinhardt
05d14cf3e2 Add new EventWrapper constructor that takes a Tick value
and schedules the event immediately.

--HG--
extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
2007-05-20 21:43:01 -07:00
Gabe Black
a13d5af274 Merge zizzer.eecs.umich.edu:/bk/newmem
into  doughnut.mwconnections.com:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
2007-05-18 13:36:47 -07:00
Gabe Black
6a6e62014e Changes to make simple cpu handle pcs appropriately for x86
--HG--
extra : convert_revision : cf68886d53301e0a63705247bd7d66b2ff08ea84
2007-05-18 10:42:50 -07:00
Gabe Black
debf04aef1 Make sure all addresses used in syscalls are truncated to 32 bits. Actually -all- arguements are truncated to 32 bits, but we should be able to get away with it.
--HG--
extra : convert_revision : 3b8766c68a4ab36e2e769fac4812657f3f7e0d1c
2007-05-12 15:11:44 -07:00
Gabe Black
6d199f0b25 Merge zizzer.eecs.umich.edu:/bk/newmem
into  doughnut.mwconnections.com:/home/gblack/newmem-o3-micro

--HG--
extra : convert_revision : 56c2205cdbb9af64c30b381a80b4d14c97841da7
2007-05-09 22:04:58 -07:00
Gabe Black
4ad1b58fdd Merge zizzer.eecs.umich.edu:/bk/newmem
into  doughnut.mwconnections.com:/home/gblack/newmem-o3-micro

--HG--
extra : convert_revision : 545b9e98eb1895f4b9e782224fb6615c71ed6323
2007-05-09 20:50:46 -07:00
Ali Saidi
37b45e3c8c fix the translating ports so it can add a page on a fault
--HG--
extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
2007-05-09 15:37:46 -04:00
Ali Saidi
a38c79ec22 the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space
fix the timing cpu to handle receiving a nacked packet

src/cpu/simple/timing.cc:
    make the timing cpu handle receiving a nacked packet
src/mem/bridge.cc:
src/mem/bridge.hh:
    the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space

--HG--
extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a
2007-05-07 18:58:38 -04:00
Kevin Lim
092951e2b1 Remove extra delete that was causing segfault.
--HG--
extra : convert_revision : 8a27ed80308c95988f3bc43d670dc0ac9e946d39
2007-04-26 00:07:42 -04:00
Kevin Lim
15cc194d71 Remove unnecessary check.
--HG--
extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b
2007-04-26 00:02:37 -04:00
Ron Dreslinski
3eb4ba3abb Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head

--HG--
extra : convert_revision : 11df5fb2a8f1fa020d042e75b22a7f2f2bcbd9ab
2007-04-23 14:38:04 -04:00
Gabe Black
cca881a531 Merge zizzer.eecs.umich.edu:/n/wexford/x/gblack/m5/newmem-o3-spec
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro

--HG--
extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
2007-04-23 15:34:40 +00:00
Gabe Black
a006aa067a Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b
2007-04-23 11:34:39 -04:00
Kevin Lim
dbc1edd23d Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head

--HG--
extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
2007-04-22 15:31:33 -04:00
Kevin Lim
8c7a6e1654 Use proper cycles for IPC and CPI equations.
src/cpu/o3/cpu.cc:
    Use proper cycles for these equations.

--HG--
extra : convert_revision : cd49410eed978c789d788e80462abed6cb89fbae
2007-04-22 15:11:54 -04:00
Gabe Black
acc62514b1 Make the floating point zero register special handling only apply for ALPHA.
--HG--
extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
2007-04-22 17:50:43 +00:00
Ali Saidi
53ba34391f fixes for solaris compile
--HG--
extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
2007-04-21 19:11:38 -04:00
Ron Dreslinski
2952c34096 Fixes for splash, may conflict with Korey's SMT work and doesn't support 03cpu yet.
src/cpu/simple/base.cc:
    Cpu's should start as unallocated, not suspended
src/cpu/simple_thread.cc:
    Wait for a thread to be assigned to activate the cpu
src/kern/tru64/tru64.hh:
    When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one.

--HG--
extra : convert_revision : 5e3ad2e96b4a715ed38293ceaccff5b9f4ea7985
2007-04-16 11:31:54 -04:00
Gabe Black
8248af53b1 Make an inner loop which pulls microops out of macroops. These aren't checked for control flow because we can pull out microops until we run out of buffer. This prevents microops from being interpretted as branches because the pc doesn't become npc.
--HG--
extra : convert_revision : 9fff7c6c32900692bbc567ecb75701c9c73da259
2007-04-15 21:52:38 +00:00
Gabe Black
308b2f0ce3 Add extra constructors to Alpha and MIPS
--HG--
extra : convert_revision : 26ea87bfe9e5c27134eb9a15bf9e4629afae6c69
2007-04-15 21:51:05 +00:00
Gabe Black
c3081d9c1c Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
--HG--
extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
2007-04-14 17:13:18 +00:00
Gabe Black
c7f1cf1d58 Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
--HG--
extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
2007-04-13 13:59:31 +00:00
Gabe Black
c382bdf93d Use a computed mask to mask out the fetch address and not a hard coded one.
--HG--
extra : convert_revision : c22907bed4b83f0dff51d2283dafe4f76fa9e94a
2007-04-11 14:16:54 +00:00
Gabe Black
54abc8b337 Make the itlb set the PHYSICAL flag on a request when it translates it. This gets it out of the cpu.
--HG--
extra : convert_revision : 20611263b799b5e835116adbf39d2ecc78701eef
2007-04-11 14:02:03 +00:00
Gabe Black
fcc35a67e0 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : c5275ef3e53393496a2ebe05b2f516884bb392f9
2007-04-10 17:27:33 +00:00
Gabe Black
74122c04cf Even if you don't want to fetch more bytes, make sure you handle a fault.
--HG--
extra : convert_revision : cfebc877b9b2ebc8927ce8267867eb40ad6d59c6
2007-04-10 17:27:12 +00:00
Gabe Black
5476247623 Fixed a compile error.
--HG--
extra : convert_revision : 70221349a7100c89be0d03210f3b04950370583f
2007-04-10 01:52:38 +00:00
Kevin Lim
64b4572c3e Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head

--HG--
extra : convert_revision : a250eed999be9b8acd6f420fdfe8f1b02905beb1
2007-04-09 14:30:49 -04:00
Kevin Lim
0cc343d41d Fix bug when blocking due to no free registers.
--HG--
extra : convert_revision : a1a218d3294515184689041487057495223360b7
2007-04-09 14:29:59 -04:00
Gabe Black
c7bb106886 Take into account that the flattened integer register space is a different size than the architected one. Also fixed some asserts.
--HG--
extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
2007-04-08 23:31:11 +00:00
Gabe Black
3bb5fd8c44 Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
2007-04-08 01:42:42 +00:00
Gabe Black
a664017c2a Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4
2007-04-04 20:50:49 +00:00
Kevin Lim
3d2a434e42 Updates for other ISA cpu_builders.
--HG--
extra : convert_revision : b02736c627bb9dcf87463a9133e04369b9f8fae2
2007-04-04 16:50:48 -04:00
Kevin Lim
6ff6621f20 Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
src/cpu/o3/alpha/cpu_impl.hh:
    Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.

--HG--
extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
2007-04-04 15:38:59 -04:00
Gabe Black
10fe8b05db Made the "data" field of store queue entries into a character array. It's sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    fixed twin memory operations.

--HG--
extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
2007-04-03 22:53:26 +00:00
Kevin Lim
98c8cd0b36 Fix a memory leak. Hopefully this fixes the longer running benchmarks.
--HG--
extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
2007-04-03 14:25:24 -04:00
Kevin Lim
ec09e5ad6f Remove/comment out DPRINTFs that were causing a segfault.
The removed ones were unnecessary.  The commented out ones could be useful in the future, should this problem get fixed.  See flyspray task #243.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
    Remove/comment out DPRINTFs that were causing a segfault.

--HG--
extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
2007-04-02 13:55:45 -04:00
Kevin Lim
24cc5227af Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.
--HG--
extra : convert_revision : ec2a739f1da07f0922c772e6998017995115ce80
2007-04-02 13:28:17 -04:00
Kevin Lim
80af6530f6 Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.

--HG--
extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
2007-03-29 12:02:57 -04:00
Kevin Lim
5c044cf1f6 Update for new trace data behavior.
--HG--
extra : convert_revision : c3df20c5187614febc4cc9f4d4c68bfecfba1ea7
2007-03-24 23:47:14 -05:00
Kevin Lim
047f77102b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
    Hand merge.  Line is no longer needed because it's handled in the ISA.

--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23 13:20:19 -04:00
Kevin Lim
941d3168d0 Updates for commit.
1. Move interrupt handling to a separate function to clean up main commit() function a bit.  Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode.
2. Better handling of updating instruction's status bits.  Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults).
3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle.  The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.

src/cpu/o3/commit.hh:
    Slightly modify how interrupts are handled.  Also include some extra bools to keep track of state properly.
src/cpu/o3/commit_impl.hh:
    Slightly modify how interrupts are handled.  Also include some extra bools to keep track of state.

    General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty.

--HG--
extra : convert_revision : 682ec6ccf4ee6ed0c8a030ceaba1c90a3619d102
2007-03-23 13:13:10 -04:00
Kevin Lim
e21878c3f2 Handle status bits a little better, as well as non-speculative instructions.
src/cpu/o3/iew_impl.hh:
    Allow for slightly more flexible handling of non-speculative instructions.  They can be other classes now, such as loads or stores.

    Also be sure to clear the state associated with squashes that are not used.  i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation.

    Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load.
src/cpu/o3/inst_queue_impl.hh:
    Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction.  This prevents non-speculative instructions from being issued too early.
src/cpu/o3/mem_dep_unit_impl.hh:
    Clear instruction's ability to issue if it's replayed.

--HG--
extra : convert_revision : d69dae878a30821222885485f4dee87170d56eb3
2007-03-23 11:40:53 -04:00
Kevin Lim
31e78b0b92 Two fixes:
1. Requests are handled more properly now.  They assume the memory system takes control of the request upon sending out an access.
2. load-load ordering is maintained.

src/cpu/base_dyn_inst.hh:
    Update how requests are handled.  The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.

    Also include some functions to allow certain status bits to be cleared.
src/cpu/base_dyn_inst_impl.hh:
    Update how requests are handled.  The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
src/cpu/o3/fetch_impl.hh:
    General correctness fixes.  retryPkt is not necessarily always set, so handle it properly.  Also consider the cache unblocked only when recvRetry is called.
src/cpu/o3/lsq_unit.hh:
    Handle requests a little more correctly.  Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system.

    Also be sure to not store-load forward from an uncacheable store.
src/cpu/o3/lsq_unit_impl.hh:
    Check to make sure load-load ordering was maintained.

    Also handle requests a little more correctly.

--HG--
extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
2007-03-23 11:33:08 -04:00
Kevin Lim
abb07d9da3 Set progress_interval in terms of CPU cycles.
--HG--
extra : convert_revision : 76b0918276cb613eb314ab1479b5ffdb31f31dee
2007-03-23 11:26:30 -04:00
Kevin Lim
55a45d3644 A couple of minor fixes.
1. Set CPU ID in all modes for the O3 CPU.
2. Use nextCycle() function to prevent phase drift in O3 CPU.
3. Remove assertion in rename map that is no longer true.

src/cpu/o3/alpha/cpu_builder.cc:
    Allow for CPU id in all modes, not just full system.  Also include a parameter that was left out by accident.
src/cpu/o3/alpha/cpu_impl.hh:
    Set the CPU ID properly.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces.
src/cpu/o3/rename_map.cc:
    Remove assertion that is no longer true.
tests/configs/o3-timing.py:
    Set CPU's id to 0.

--HG--
extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
2007-03-23 11:22:43 -04:00
Gabe Black
63e2d3dcbf Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 41214c71e7fa11d47395975a141793337d020463
2007-03-21 01:18:55 -04:00
Gabe Black
2b4c02b829 The m5 side of statetrace. This is fairly ugly, but I don't want to lose it.
--HG--
extra : convert_revision : 171b41418567c1f41f43363a46fa9aeaa58ae606
2007-03-21 01:18:47 -04:00
Gabe Black
7c0825ccf9 Compile fixes for SPARC_FS.
src/arch/alpha/predecoder.hh:
src/arch/sparc/predecoder.hh:
    Put in a missing include
src/cpu/exetrace.cc:
    Convert the legion lockstep stuff from makeExtMI to the predecoder object.

--HG--
extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
2007-03-18 23:09:51 -04:00
Gabe Black
725ee42ba7 Fix ALPHA_FS compile. The MachInst -> StaticInstPtr constructor is no longer a conversion constructor because it caused ambiguous conversions when setting the pointer to NULL.
--HG--
extra : convert_revision : ce9ecfc03a47642d105f2378208bbe923d6b765b
2007-03-16 10:57:34 +00:00
Ali Saidi
c6e1dc61c2 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 6a75fa02391c4c65063c5412a568705bb1dd892b
2007-03-15 15:16:35 -04:00
Gabe Black
32368a2bd6 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
    Hand merge

--HG--
extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
2007-03-15 02:52:51 +00:00
Gabe Black
a2b56088fb Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
    Make the predecoder an object with it's own switched header file.

--HG--
extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-15 02:47:42 +00:00
Ali Saidi
c6188a2264 fix segfault when peer owner attempts to use functional port
--HG--
extra : convert_revision : 3702b4bd038a59bff823c3b428fdfbaabc9715df
2007-03-13 17:34:52 -04:00
Gabe Black
ff90b8c1aa Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
2007-03-13 15:03:34 -04:00
Gabe Black
ce18d900a1 Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.

--HG--
extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
2007-03-13 16:13:21 +00:00
Ali Saidi
a068d6db0f fix interrupting during a quisce on sparc
src/arch/sparc/ua2005.cc:
    fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
    check if were suspended and interrupt at the guess time
src/base/traceflags.py:
    add trace flag for Iob
src/cpu/simple/base.cc:
    Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
    add some Dprintfs

--HG--
extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
2007-03-13 00:05:52 -04:00
Ron Dreslinski
c6e85efc50 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head

--HG--
extra : convert_revision : 7d7380a6565cff32470bddadb0158fad897a5cf5
2007-03-12 16:25:59 -05:00
Ali Saidi
8d38dd3231 remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault
--HG--
extra : convert_revision : 5e4c2ec753372fd0569734d3ddb0c8690409ca16
2007-03-12 17:23:08 -04:00
Ron Dreslinski
6415c47a5b Fix some of the memory leaks related to writebacks
src/cpu/memtest/memtest.cc:
    Add the [] to a delete to make it work correctly
src/mem/cache/cache_impl.hh:
    Fix one of the memory leaks

--HG--
extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7
2007-03-12 13:15:32 -05:00
Gabe Black
6a7e4a5904 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 725999a0a5bde6e065bad87b42e973c5c627c69f
2007-03-11 18:19:38 -04:00
Gabe Black
26c0426e44 Make sttw and sttwa use the twin memory operations.
--HG--
extra : convert_revision : 368d1c57a46fd5ca15461cb5ee8e05fd1e080daa
2007-03-11 18:12:33 -04:00
Nathan Binkert
1aef5c06a3 Rework the way SCons recurses into subdirectories, making it
automatic.  The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes.  On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory.  On the second pass,
all subdirs of the src directory are searched for SConscript
files.  These files describe how to build any given subdirectory.
I have added a Source() function.  Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build.  Clean up everything to take
advantage of Source().
function is added to the list of files to be built.

--HG--
extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-10 23:00:54 -08:00
Ali Saidi
ef6dfc2983 I thought this code got deleted, but since it hasn't I've moved it to a place where it doesn't access freed memory.
--HG--
extra : convert_revision : 4d9023f6193004a3e9cbeebd3721bccb50b2aab0
2007-03-10 15:00:41 -05:00
Kevin Lim
ad44834907 Two fixes:
1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed.  This is done by making setPeer() virtual, and overriding it in the CPU's ports.  When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts().
2. Consolidate redundant code that handles switching in a CPU.

src/cpu/base.cc:
    Move common code of switching over peers to base CPU.
src/cpu/base.hh:
    Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
    Add in function that updates thread context's ports.
    Also use updated function to takeOverFrom() in BaseCPU.  This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
    Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
    Add function to dcache port that will update the memory ports upon getting a new peer.
    Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
    Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Add function that will update thread context's memory ports upon getting a new peer.
    Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
    Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
    Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
    Make setPeer virtual so that other classes can override it.

--HG--
extra : convert_revision : 2050f1241dd2e83875d281cfc5ad5c6c8705fdaf
2007-03-09 10:06:09 -05:00
Ali Saidi
027dfa01e6 stop m5 from leaking like a sieve
don't create a new physPort/virtPort every time activateContext() is called
add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs()
on the port owner as well as delete it's peer
still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic

src/cpu/thread_state.cc:
    if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it
src/mem/bus.cc:
src/mem/bus.hh:
    add ability to delete a port by usig a hash_map instead of an array to store port ids
    add a function to do deleting
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/mem_object.cc:
src/mem/mem_object.hh:
    adda function to delete port references from a memory object
src/mem/port.cc:
src/mem/port.hh:
    add a removeConn function that tell the owener to delete any references to the port and then deletes its peer

--HG--
extra : convert_revision : 272f0c8f80e1cf1ab1750d8be5a6c9aa110b06a4
2007-03-08 18:57:15 -05:00
Ali Saidi
87fb0eb8de I missed a couple of WithEffects, this should do it
--HG--
extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
2007-03-07 21:51:44 -05:00
Gabe Black
8edc9d79ce Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89
2007-03-07 20:04:45 +00:00
Ali Saidi
689cab36c9 *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
2007-03-07 15:04:31 -05:00
Gabe Black
c822513269 Add setData functions for the new Twin??_t types.
--HG--
extra : convert_revision : 6f4e08e76eb4a95eb08b11632f6e33ba458723b6
2007-03-07 17:46:06 +00:00
Nathan Binkert
d55b25cde6 Move all of the parameters of the Root SimObject so they are
directly configured by python.  Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-06 11:13:43 -08:00
Gabe Black
d539052b63 Add x86 version of call to "decode"
--HG--
extra : convert_revision : bb799dcea58b51d6e1d3d744581ea48c5c1490fe
2007-03-05 16:13:50 +00:00
Gabe Black
c7ab9f5bb2 Added an x86 dyninst
--HG--
extra : convert_revision : 2317e9bb0bcf8010ab5d02019f7a14eeb7b1459c
2007-03-05 14:55:45 +00:00
Ali Saidi
82874eefca Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03 19:03:22 -05:00
Ali Saidi
36f43ff6a5 Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 17:22:47 -05:00
Ali Saidi
4e8d2d1593 make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
    make ldtw(a) Twin 32 bit load work correctly

--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
2007-03-02 22:34:51 -05:00
Gabe Black
29e5df890d Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
--HG--
extra : convert_revision : ea873f01c62234c0542f310cc143c6a7c76ade94
2007-02-28 16:36:38 +00:00