Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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@ -48,17 +48,19 @@ namespace AlphaISA
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return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
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}
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static inline ExtMachInst
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makeExtMI(MachInst inst, Addr pc) {
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enum PredecodeResult {
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MoreBytes = 1,
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ExtMIReady = 2
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};
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static inline unsigned int
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predecode(ExtMachInst & ext_inst, Addr pc, MachInst inst, ThreadContext *) {
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ext_inst = inst;
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#if FULL_SYSTEM
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ExtMachInst ext_inst = inst;
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if (pc && 0x1)
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return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
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else
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return ext_inst;
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#else
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return ExtMachInst(inst);
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ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
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#endif
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return MoreBytes | ExtMIReady;
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}
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inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -27,6 +28,7 @@
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Korey Sewell
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*/
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#ifndef __ARCH_MIPS_UTILITY_HH__
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@ -86,17 +88,15 @@ namespace MipsISA {
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return 0;
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}
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static inline ExtMachInst
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makeExtMI(MachInst inst, ThreadContext * xc) {
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#if FULL_SYSTEM
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ExtMachInst ext_inst = inst;
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if (xc->readPC() && 0x1)
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return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
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else
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return ext_inst;
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#else
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return ExtMachInst(inst);
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#endif
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enum PredecodeResult {
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MoreBytes = 1,
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ExtMIReady = 2
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};
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static inline unsigned int
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predecode(ExtMachInst &emi, Addr, MachInst inst, ThreadContext *) {
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emi = inst;
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return MoreBytes | ExtMIReady;
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}
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};
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@ -48,9 +48,15 @@ namespace SparcISA
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tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
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}
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inline ExtMachInst
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makeExtMI(MachInst inst, ThreadContext * xc) {
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ExtMachInst emi = (MachInst) inst;
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enum PredecodeResult {
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MoreBytes = 1,
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ExtMIReady = 2
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};
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inline unsigned int
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predecode(ExtMachInst &emi, Addr currPC, MachInst inst,
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ThreadContext * xc) {
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emi = inst;
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//The I bit, bit 13, is used to figure out where the ASI
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//should come from. Use that in the ExtMachInst. This is
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//slightly redundant, but it removes the need to put a condition
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@ -61,7 +67,7 @@ namespace SparcISA
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else
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emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
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<< (sizeof(MachInst) * 8));
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return emi;
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return MoreBytes | ExtMIReady;
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}
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inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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@ -62,10 +62,19 @@
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namespace X86ISA
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{
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//XXX This won't work
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typedef uint32_t MachInst;
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//XXX This won't work either
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typedef uint64_t ExtMachInst;
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//This really determines how many bytes are passed to the predecoder.
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typedef uint64_t MachInst;
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//The intermediate structure the x86 predecoder returns.
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struct ExtMachInst
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{
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//Empty for now...
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};
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bool operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
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{
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//Since this is empty, it's always equal
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return true;
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}
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typedef uint64_t IntReg;
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//XXX Should this be a 128 bit structure for XMM memory ops?
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@ -72,9 +72,16 @@ namespace X86ISA
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return false;
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}
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inline ExtMachInst
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makeExtMI(MachInst inst, ThreadContext * xc) {
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return inst;
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PredecodeResult {
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MoreBytes = 1,
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ExtMIReady = 2
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};
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unsigned int
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predecode(ExtMachInst &extMachInst, Addr currPC, MachInst machInst,
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ThreadContext * xc) {
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//Do something to fill up extMachInst...
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return MoreBytes | ExtMIReady;
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}
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inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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@ -1117,13 +1117,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
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(&cacheData[tid][offset]));
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#if THE_ISA == ALPHA_ISA
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ext_inst = TheISA::makeExtMI(inst, fetch_PC);
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#elif THE_ISA == SPARC_ISA
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ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
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#elif THE_ISA == MIPS_ISA
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ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
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#endif
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//unsigned int result =
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TheISA::predecode(ext_inst, fetch_PC, inst,
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cpu->thread[tid]->getTC());
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// Create a new DynInst from the instruction fetched.
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DynInstPtr instruction = new DynInst(ext_inst,
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@ -367,18 +367,18 @@ BaseSimpleCPU::preExecute()
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inst = gtoh(inst);
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//If we're not in the middle of a macro instruction
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if (!curMacroStaticInst) {
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#if THE_ISA == ALPHA_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
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#elif THE_ISA == SPARC_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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#elif THE_ISA == X86_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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#elif THE_ISA == MIPS_ISA
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//Mips doesn't do anything in it's MakeExtMI function right now,
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//so it won't be called.
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StaticInstPtr instPtr = StaticInst::decode(inst);
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#endif
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if (instPtr->isMacroOp()) {
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StaticInstPtr instPtr = NULL;
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//Predecode, ie bundle up an ExtMachInst
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unsigned int result =
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predecode(extMachInst, thread->readPC(), inst, thread->getTC());
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//If an instruction is ready, decode it
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if (result & ExtMIReady)
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instPtr = StaticInst::decode(extMachInst);
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//If we decoded an instruction and it's microcoded, start pulling
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//out micro ops
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if (instPtr && instPtr->isMacroOp()) {
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->
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fetchMicroOp(thread->readMicroPC());
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@ -391,17 +391,19 @@ BaseSimpleCPU::preExecute()
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fetchMicroOp(thread->readMicroPC());
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}
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//If we decoded an instruction this "tick", record information about it.
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if(curStaticInst)
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{
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
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curStaticInst->getName(), curStaticInst->getOpcode(),
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curStaticInst->machInst);
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DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
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curStaticInst->getName(), curStaticInst->machInst);
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#if FULL_SYSTEM
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thread->setInst(inst);
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thread->setInst(inst);
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#endif // FULL_SYSTEM
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}
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}
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void
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@ -74,7 +74,6 @@ namespace Trace {
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class BaseSimpleCPU : public BaseCPU
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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#endif
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// current instruction
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MachInst inst;
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TheISA::MachInst inst;
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// current extended machine instruction
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TheISA::ExtMachInst extMachInst;
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// Static data storage
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TheISA::LargestRead dataReg;
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@ -439,9 +439,6 @@ class StaticInst : public StaticInstBase
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//This is defined as inline below.
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static StaticInstPtr decode(ExtMachInst mach_inst);
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/// Return opcode of machine instruction
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uint32_t getOpcode() { return bits(machInst, 31, 26);}
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/// Return name of machine instruction
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std::string getName() { return mnemonic; }
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};
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/// Construct directly from machine instruction.
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/// Calls StaticInst::decode().
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StaticInstPtr(TheISA::ExtMachInst mach_inst)
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explicit StaticInstPtr(TheISA::ExtMachInst mach_inst)
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: RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
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{
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}
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