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Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst.

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src/arch/x86/predecoder.cc:
    Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.

--HG--
extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
This commit is contained in:
Gabe Black 2007-06-13 20:09:03 +00:00
parent 5fd567425d
commit cd8f604cc9
8 changed files with 28 additions and 49 deletions
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11
src/arch/alpha/predecoder.hh
View file

@ -69,9 +69,9 @@ namespace AlphaISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr off, MachInst inst)
void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst)
{
fetchPC = pc;
fetchPC = _fetchPC;
assert(off == 0);
ext_inst = inst;
#if FULL_SYSTEM
@ -80,13 +80,6 @@ namespace AlphaISA
#endif
}
//Use this to give data to the predecoder. This should be used
//when instructions are executed in order.
void moreBytes(MachInst machInst)
{
moreBytes(fetchPC + sizeof(machInst), 0, machInst);
}
bool needMoreBytes()
{
return true;

9
src/arch/mips/predecoder.hh
View file

@ -66,19 +66,12 @@ namespace MipsISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr currPC, Addr off, MachInst inst)
void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
{
assert(off == 0);
emi = inst;
}
//Use this to give data to the predecoder. This should be used
//when instructions are executed in order.
void moreBytes(MachInst machInst)
{
moreBytes(0, 0, machInst);
}
bool needMoreBytes()
{
return true;

9
src/arch/sparc/predecoder.hh
View file

@ -67,7 +67,7 @@ namespace SparcISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr currPC, Addr off, MachInst inst)
void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
{
assert(off == 0);
@ -85,13 +85,6 @@ namespace SparcISA
<< (sizeof(MachInst) * 8));
}
//Use this to give data to the predecoder. This should be used
//when instructions are executed in order.
void moreBytes(MachInst machInst)
{
moreBytes(0, 0, machInst);
}
bool needMoreBytes()
{
return true;

22
src/arch/x86/predecoder.cc
View file

@ -209,34 +209,38 @@ namespace X86ISA
//Figure out the effective operand size. This can be overriden to
//a fixed value at the decoder level.
int logOpSize;
if(/*FIXME long mode*/1)
{
if(emi.rex && emi.rex.w)
emi.opSize = 3; // 64 bit operand size
if(emi.rex.w)
logOpSize = 3; // 64 bit operand size
else if(emi.legacy.op)
emi.opSize = 1; // 16 bit operand size
logOpSize = 1; // 16 bit operand size
else
emi.opSize = 2; // 32 bit operand size
logOpSize = 2; // 32 bit operand size
}
else if(/*FIXME default 32*/1)
{
if(emi.legacy.op)
emi.opSize = 1; // 16 bit operand size
logOpSize = 1; // 16 bit operand size
else
emi.opSize = 2; // 32 bit operand size
logOpSize = 2; // 32 bit operand size
}
else // 16 bit default operand size
{
if(emi.legacy.op)
emi.opSize = 2; // 32 bit operand size
logOpSize = 2; // 32 bit operand size
else
emi.opSize = 1; // 16 bit operand size
logOpSize = 1; // 16 bit operand size
}
//Figure out how big of an immediate we'll retreive based
//on the opcode.
int immType = ImmediateType[emi.opcode.num - 1][nextByte];
immediateSize = SizeTypeToSize[emi.opSize - 1][immType];
immediateSize = SizeTypeToSize[logOpSize - 1][immType];
//Set the actual op size
emi.opSize = 1 << logOpSize;
//Determine what to expect next
if (UsesModRM[emi.opcode.num - 1][nextByte]) {

11
src/arch/x86/predecoder.hh
View file

@ -192,9 +192,9 @@ namespace X86ISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr currPC, Addr off, MachInst data)
void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data)
{
basePC = currPC;
basePC = fetchPC;
offset = off;
fetchChunk = data;
assert(off < sizeof(MachInst));
@ -202,13 +202,6 @@ namespace X86ISA
process();
}
//Use this to give data to the predecoder. This should be used
//when instructions are executed in order.
void moreBytes(MachInst machInst)
{
moreBytes(basePC + sizeof(machInst), 0, machInst);
}
bool needMoreBytes()
{
return outOfBytes;

2
src/cpu/o3/fetch_impl.hh
View file

@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
(&cacheData[tid][offset]));
predecoder.setTC(cpu->thread[tid]->getTC());
predecoder.moreBytes(fetch_PC, 0, inst);
predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
ext_inst = predecoder.getExtMachInst();

10
src/cpu/simple/base.cc
View file

@ -336,13 +336,12 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
thread->readNextPC(),thread->readNextNPC());
#else
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
thread->readNextPC());
#endif
const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
Addr fetchPC = threadPC + fetchOffset;
req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
Addr fetchPC = (threadPC & PCMask) + fetchOffset;
req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
Fault fault = thread->translateInstReq(req);
@ -381,7 +380,8 @@ BaseSimpleCPU::preExecute()
predecoder.setTC(thread->getTC());
//If more fetch data is needed, pass it in.
if(predecoder.needMoreBytes())
predecoder.moreBytes(thread->readPC() + fetchOffset, 0, inst);
predecoder.moreBytes(thread->readPC(),
(thread->readPC() & PCMask) + fetchOffset, 0, inst);
else
predecoder.process();

3
src/cpu/simple/base.hh
View file

@ -166,6 +166,9 @@ class BaseSimpleCPU : public BaseCPU
return numInst - startNumInst;
}
// Mask to align PCs to MachInst sized boundaries
static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
// number of simulated memory references
Stats::Scalar<> numMemRefs;