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gem5/src/cpu
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Steve Reinhardt 57ff2604e5 Minor fix plus new assertion to catch similar bugs. 
src/cpu/memtest/memtest.cc:
    Need to set packet source field so that response from cache
    doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
    Copy source field when copying packets.
    Assert that source is valid before copying it to dest
    when turning packets around.

--HG--
extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
2007-06-23 13:24:33 -07:00
..
checker *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
memtest Minor fix plus new assertion to catch similar bugs. 2007-06-23 13:24:33 -07:00
o3 Merge zizzer.eecs.umich.edu:/bk/newmem 2007-06-21 20:35:25 +00:00
ozone Fix cut-n-pasto to make the path correct 2007-05-30 17:19:20 -07:00
simple Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. 2007-06-19 18:17:34 +00:00
trace Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00
activity.cc make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
activity.hh Update copyright. 2006-06-07 16:02:55 -04:00
base.cc Removed "adding instead of dividing" trick. 2007-06-20 14:54:17 -04:00
base.hh Merge zizzer.eecs.umich.edu:/bk/newmem 2007-03-15 02:52:51 +00:00
base_dyn_inst.hh Fix compiler errors. 2007-06-20 19:46:45 -07:00
base_dyn_inst_impl.hh Fix compiler errors. 2007-06-20 19:46:45 -07:00
BaseCPU.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
cpu_models.py Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst. 2006-07-06 12:18:55 -04:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh Make SPARC checkpointing work 2007-01-30 18:25:39 -05:00
exec_context.hh *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
exetrace.cc Missed an "offset" to get rid of. 2007-06-19 19:01:02 +00:00
exetrace.hh Add setData functions for the new Twin??_t types. 2007-03-07 17:46:06 +00:00
func_unit.cc Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory. 2006-06-16 17:52:15 -04:00
func_unit.hh Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory. 2006-06-16 17:52:15 -04:00
FuncUnit.py Rename enum from OpType to OpClass so it's consistent with the 2007-06-11 23:10:58 -07:00
inst_seq.hh fixes so that M5 will compile under solaris 2006-11-04 21:41:01 -05:00
intr_control.cc Implement Niagara I/O interface and rework interrupts 2007-03-03 17:22:47 -05:00
intr_control.hh Implement Niagara I/O interface and rework interrupts 2007-03-03 17:22:47 -05:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
op_class.cc Rename enum from OpType to OpClass so it's consistent with the 2007-06-11 23:10:58 -07:00
op_class.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
pc_event.cc remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault 2007-03-12 17:23:08 -04:00
pc_event.hh Added sim/host.hh for the Addr type. 2006-11-07 05:42:15 -05:00
profile.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
profile.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
quiesce_event.cc Add Quiesce trace flag to track CPU quiesce/wakeup events. 2006-10-21 23:32:14 -07:00
quiesce_event.hh Update copyright. 2006-06-07 16:02:55 -04:00
SConscript Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
simple_thread.cc Fixes for splash, may conflict with Korey's SMT work and doesn't support 03cpu yet. 2007-04-16 11:31:54 -04:00
simple_thread.hh Remove unnecessary include of physical.hh. 2007-05-28 08:03:13 -07:00
smt.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
static_inst.cc Modified instruction decode method. 2007-06-14 16:52:19 -04:00
static_inst.hh Modified instruction decode method. 2007-06-14 16:52:19 -04:00
thread_context.hh *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
thread_state.cc fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
thread_state.hh Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00