36f43ff6a5
configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
97 lines
3.1 KiB
C++
97 lines
3.1 KiB
C++
/*
|
|
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* Authors: Nathan Binkert
|
|
* Ron Dreslinski
|
|
*/
|
|
|
|
#include <string>
|
|
#include <vector>
|
|
|
|
#include "cpu/base.hh"
|
|
#include "cpu/thread_context.hh"
|
|
#include "cpu/intr_control.hh"
|
|
#include "sim/builder.hh"
|
|
#include "sim/sim_object.hh"
|
|
|
|
using namespace std;
|
|
|
|
IntrControl::IntrControl(const string &name, System *s)
|
|
: SimObject(name), sys(s)
|
|
{}
|
|
|
|
void
|
|
IntrControl::post(int int_num, int index)
|
|
{
|
|
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
|
|
BaseCPU *temp = tcvec[0]->getCpuPtr();
|
|
temp->post_interrupt(int_num, index);
|
|
}
|
|
|
|
void
|
|
IntrControl::post(int cpu_id, int int_num, int index)
|
|
{
|
|
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
|
|
BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
|
|
temp->post_interrupt(int_num, index);
|
|
}
|
|
|
|
void
|
|
IntrControl::clear(int int_num, int index)
|
|
{
|
|
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
|
|
BaseCPU *temp = tcvec[0]->getCpuPtr();
|
|
temp->clear_interrupt(int_num, index);
|
|
}
|
|
|
|
void
|
|
IntrControl::clear(int cpu_id, int int_num, int index)
|
|
{
|
|
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
|
|
BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
|
|
temp->clear_interrupt(int_num, index);
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
|
|
|
|
SimObjectParam<System *> sys;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
|
|
|
|
INIT_PARAM(sys, "the system we are part of")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(IntrControl)
|
|
|
|
CREATE_SIM_OBJECT(IntrControl)
|
|
{
|
|
return new IntrControl(getInstanceName(), sys);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("IntrControl", IntrControl)
|