Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
src/SConscript:
Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
Include the func unit file that's not in the encumbered directory.
--HG--
extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241
This commit is contained in:
Kevin Lim
parent
def9ea38b5
commit
0bbd909f02
5 changed files with 291 additions and 3 deletions
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@ -85,6 +85,7 @@ base_sources = Split('''
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cpu/base.cc
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cpu/cpuevent.cc
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cpu/exetrace.cc
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cpu/func_unit.cc
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cpu/op_class.cc
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cpu/pc_event.cc
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cpu/quiesce_event.cc
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@ -93,8 +94,6 @@ base_sources = Split('''
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cpu/simple_thread.cc
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cpu/thread_state.cc
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encumbered/cpu/full/fu_pool.cc
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mem/bridge.cc
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mem/bus.cc
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mem/connector.cc
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171
src/cpu/func_unit.cc
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171
src/cpu/func_unit.cc
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@ -0,0 +1,171 @@
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/*
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* Copyright (c) 2002-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Raasch
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*/
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#include <sstream>
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#include "base/misc.hh"
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#include "cpu/func_unit.hh"
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#include "sim/builder.hh"
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using namespace std;
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////////////////////////////////////////////////////////////////////////////
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//
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// The funciton unit
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//
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FuncUnit::FuncUnit()
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{
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capabilityList.reset();
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}
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// Copy constructor
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FuncUnit::FuncUnit(const FuncUnit &fu)
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{
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for (int i = 0; i < Num_OpClasses; ++i) {
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opLatencies[i] = fu.opLatencies[i];
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issueLatencies[i] = fu.issueLatencies[i];
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}
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capabilityList = fu.capabilityList;
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}
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void
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FuncUnit::addCapability(OpClass cap, unsigned oplat, unsigned issuelat)
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{
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if (issuelat == 0 || oplat == 0)
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panic("FuncUnit: you don't really want a zero-cycle latency do you?");
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capabilityList.set(cap);
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opLatencies[cap] = oplat;
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issueLatencies[cap] = issuelat;
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}
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bool
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FuncUnit::provides(OpClass capability)
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{
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return capabilityList[capability];
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}
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bitset<Num_OpClasses>
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FuncUnit::capabilities()
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{
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return capabilityList;
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}
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unsigned &
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FuncUnit::opLatency(OpClass cap)
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{
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return opLatencies[cap];
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}
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unsigned
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FuncUnit::issueLatency(OpClass capability)
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{
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return issueLatencies[capability];
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}
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////////////////////////////////////////////////////////////////////////////
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//
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// The SimObjects we use to get the FU information into the simulator
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//
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////////////////////////////////////////////////////////////////////////////
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//
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// We use 2 objects to specify this data in the INI file:
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// (1) OpDesc - Describes the operation class & latencies
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// (multiple OpDesc objects can refer to the same
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// operation classes)
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// (2) FUDesc - Describes the operations available in the unit &
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// the number of these units
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//
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//
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//
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// The operation-class description object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
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SimpleEnumParam<OpClass> opClass;
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Param<unsigned> opLat;
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Param<unsigned> issueLat;
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END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
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BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
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INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
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INIT_PARAM(opLat, "cycles until result is available"),
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INIT_PARAM(issueLat, "cycles until another can be issued")
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END_INIT_SIM_OBJECT_PARAMS(OpDesc)
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CREATE_SIM_OBJECT(OpDesc)
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{
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return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
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}
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REGISTER_SIM_OBJECT("OpDesc", OpDesc)
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//
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// The FuDesc object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
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SimObjectVectorParam<OpDesc *> opList;
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Param<unsigned> count;
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END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
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BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
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INIT_PARAM(opList, "list of operation classes for this FU type"),
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INIT_PARAM(count, "number of these FU's available")
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END_INIT_SIM_OBJECT_PARAMS(FUDesc)
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CREATE_SIM_OBJECT(FUDesc)
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{
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return new FUDesc(getInstanceName(), opList, count);
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}
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REGISTER_SIM_OBJECT("FUDesc", FUDesc)
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101
src/cpu/func_unit.hh
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101
src/cpu/func_unit.hh
Normal file
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@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2002-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Raasch
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*/
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#ifndef __CPU_FUNC_UNIT_HH__
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#define __CPU_FUNC_UNIT_HH__
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#include <bitset>
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#include <string>
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#include <vector>
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#include "cpu/op_class.hh"
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#include "sim/sim_object.hh"
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////////////////////////////////////////////////////////////////////////////
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//
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// Structures used ONLY during the initialization phase...
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//
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//
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//
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struct OpDesc : public SimObject
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{
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OpClass opClass;
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unsigned opLat;
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unsigned issueLat;
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OpDesc(std::string name, OpClass c, unsigned o, unsigned i)
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: SimObject(name), opClass(c), opLat(o), issueLat(i) {};
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};
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struct FUDesc : public SimObject
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{
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std::vector<OpDesc *> opDescList;
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unsigned number;
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FUDesc(std::string name, std::vector<OpDesc *> l, unsigned n)
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: SimObject(name), opDescList(l), number(n) {};
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};
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typedef std::vector<OpDesc *>::iterator OPDDiterator;
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typedef std::vector<FUDesc *>::iterator FUDDiterator;
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////////////////////////////////////////////////////////////////////////////
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//
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// The actual FU object
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//
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//
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//
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class FuncUnit
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{
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private:
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unsigned opLatencies[Num_OpClasses];
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unsigned issueLatencies[Num_OpClasses];
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std::bitset<Num_OpClasses> capabilityList;
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public:
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FuncUnit();
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FuncUnit(const FuncUnit &fu);
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std::string name;
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void addCapability(OpClass cap, unsigned oplat, unsigned issuelat);
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bool provides(OpClass capability);
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std::bitset<Num_OpClasses> capabilities();
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unsigned &opLatency(OpClass capability);
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unsigned issueLatency(OpClass capability);
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};
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#endif // __FU_POOL_HH__
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@ -31,7 +31,7 @@
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#include <sstream>
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#include "cpu/o3/fu_pool.hh"
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#include "encumbered/cpu/full/fu_pool.hh"
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#include "cpu/func_unit.hh"
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#include "sim/builder.hh"
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using namespace std;
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17
src/python/m5/objects/FuncUnit.py
Normal file
17
src/python/m5/objects/FuncUnit.py
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@ -0,0 +1,17 @@
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from m5.config import *
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class OpType(Enum):
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vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
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'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
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'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
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class OpDesc(SimObject):
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type = 'OpDesc'
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issueLat = Param.Int(1, "cycles until another can be issued")
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opClass = Param.OpType("type of operation")
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opLat = Param.Int(1, "cycles until result is available")
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class FUDesc(SimObject):
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type = 'FUDesc'
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count = Param.Int("number of these FU's available")
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opList = VectorParam.OpDesc("operation classes for this FU type")
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