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Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.

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--HG--
extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
This commit is contained in:
Gabe Black 2007-06-19 18:17:34 +00:00
parent d496492793
commit ea70e6d6da
7 changed files with 15 additions and 22 deletions
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6
src/arch/alpha/predecoder.hh
View file

@ -44,8 +44,6 @@ namespace AlphaISA
{
protected:
ThreadContext * tc;
//The pc of the current instruction
Addr fetchPC;
//The extended machine instruction being generated
ExtMachInst ext_inst;
@ -69,10 +67,8 @@ namespace AlphaISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst)
void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
{
fetchPC = _fetchPC;
assert(off == 0);
ext_inst = inst;
#if FULL_SYSTEM
if (pc && 0x1)

3
src/arch/mips/predecoder.hh
View file

@ -66,9 +66,8 @@ namespace MipsISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
{
assert(off == 0);
emi = inst;
}

4
src/arch/sparc/predecoder.hh
View file

@ -67,10 +67,8 @@ namespace SparcISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
{
assert(off == 0);
emi = inst;
//The I bit, bit 13, is used to figure out where the ASI
//should come from. Use that in the ExtMachInst. This is

6
src/arch/x86/predecoder.hh
View file

@ -195,12 +195,12 @@ namespace X86ISA
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data)
void moreBytes(Addr pc, Addr fetchPC, MachInst data)
{
DPRINTF(Predecoder, "Getting more bytes.\n");
basePC = fetchPC;
offset = off;
offset = (fetchPC >= pc) ? 0 : pc - fetchPC;
fetchChunk = data;
assert(off < sizeof(MachInst));
outOfBytes = false;
process();
}

2
src/cpu/o3/fetch_impl.hh
View file

@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
(&cacheData[tid][offset]));
predecoder.setTC(cpu->thread[tid]->getTC());
predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
predecoder.moreBytes(fetch_PC, fetch_PC, inst);
ext_inst = predecoder.getExtMachInst();

6
src/cpu/simple/atomic.cc
View file

@ -521,15 +521,15 @@ AtomicSimpleCPU::tick()
dcache_access = false; // assume no dcache access
//Fetch more instruction memory if necessary
if(predecoder.needMoreBytes())
{
//if(predecoder.needMoreBytes())
//{
icache_access = true;
ifetch_pkt->reinitFromRequest();
icache_latency = icachePort.sendAtomic(ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
}
//}
preExecute();

10
src/cpu/simple/base.cc
View file

@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute()
//This should go away once the constructor can be set up properly
predecoder.setTC(thread->getTC());
//If more fetch data is needed, pass it in.
if(predecoder.needMoreBytes())
predecoder.moreBytes(thread->readPC(),
(thread->readPC() & PCMask) + fetchOffset, 0, inst);
else
predecoder.process();
Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
//if(predecoder.needMoreBytes())
predecoder.moreBytes(thread->readPC(), fetchPC, inst);
//else
// predecoder.process();
//If an instruction is ready, decode it. Otherwise, we'll have to
//fetch beyond the MachInst at the current pc.