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checker
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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memtest
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Fix some of the memory leaks related to writebacks
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2007-03-12 13:15:32 -05:00 |
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o3
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fixes for solaris compile
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2007-04-21 19:11:38 -04:00 |
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ozone
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fix segfault when peer owner attempts to use functional port
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2007-03-13 17:34:52 -04:00 |
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simple
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Even if you don't want to fetch more bytes, make sure you handle a fault.
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2007-04-10 17:27:12 +00:00 |
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trace
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Rework the way SCons recurses into subdirectories, making it
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2007-03-10 23:00:54 -08:00 |
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activity.cc
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make our code a little more standards compliant
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2007-01-26 18:48:51 -05:00 |
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activity.hh
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Update copyright.
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2006-06-07 16:02:55 -04:00 |
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base.cc
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Merge ktlim@zizzer:/bk/newmem
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2007-03-23 13:20:19 -04:00 |
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base.hh
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-15 02:52:51 +00:00 |
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base_dyn_inst.hh
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Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
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2007-04-08 01:42:42 +00:00 |
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base_dyn_inst_impl.hh
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Two fixes:
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2007-03-23 11:33:08 -04:00 |
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cpu_models.py
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Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
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2006-07-06 12:18:55 -04:00 |
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cpuevent.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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cpuevent.hh
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Make SPARC checkpointing work
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2007-01-30 18:25:39 -05:00 |
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exec_context.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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exetrace.cc
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Fixed a compile error.
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2007-04-10 01:52:38 +00:00 |
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exetrace.hh
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Add setData functions for the new Twin??_t types.
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2007-03-07 17:46:06 +00:00 |
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func_unit.cc
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Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
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2006-06-16 17:52:15 -04:00 |
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func_unit.hh
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Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
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2006-06-16 17:52:15 -04:00 |
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inst_seq.hh
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fixes so that M5 will compile under solaris
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2006-11-04 21:41:01 -05:00 |
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intr_control.cc
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Implement Niagara I/O interface and rework interrupts
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2007-03-03 17:22:47 -05:00 |
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intr_control.hh
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Implement Niagara I/O interface and rework interrupts
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2007-03-03 17:22:47 -05:00 |
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m5legion_interface.h
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add fsr to the list of registers we are interested in
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2007-01-30 18:27:04 -05:00 |
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op_class.cc
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Updated Authors from bk prs info
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2006-05-31 19:26:56 -04:00 |
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op_class.hh
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
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pc_event.cc
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remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault
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2007-03-12 17:23:08 -04:00 |
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pc_event.hh
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Added sim/host.hh for the Addr type.
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2006-11-07 05:42:15 -05:00 |
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profile.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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profile.hh
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Put the ProcessInfo and StackTrace objects into the ISA namespaces.
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2006-11-08 00:52:04 -05:00 |
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quiesce_event.cc
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Add Quiesce trace flag to track CPU quiesce/wakeup events.
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2006-10-21 23:32:14 -07:00 |
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quiesce_event.hh
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Update copyright.
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2006-06-07 16:02:55 -04:00 |
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SConscript
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Rework the way SCons recurses into subdirectories, making it
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2007-03-10 23:00:54 -08:00 |
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simple_thread.cc
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fix segfault when peer owner attempts to use functional port
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2007-03-13 17:34:52 -04:00 |
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simple_thread.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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smt.hh
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Updated Authors from bk prs info
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2006-05-31 19:26:56 -04:00 |
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static_inst.cc
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Move all of the parameters of the Root SimObject so they are
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2007-03-06 11:13:43 -08:00 |
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static_inst.hh
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Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.
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2007-03-15 02:47:42 +00:00 |
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thread_context.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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thread_state.cc
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stop m5 from leaking like a sieve
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2007-03-08 18:57:15 -05:00 |
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thread_state.hh
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Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
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2006-11-29 16:07:55 -05:00 |
