fixes for solaris compile

--HG--
extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320

src/arch/alpha/ev5.cc

@@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
         {
             AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
 
-            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
-            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
-            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
-            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
-            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
-            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
-            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
+            retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
+            retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
+            retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
+            retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
+            retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
+            retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
+            retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
         }
         break;
 

src/arch/alpha/floatregfile.hh

@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/types.hh"
 
-#include <string.h>
+#include <cstring>
 #include <iostream>
 
 class Checkpoint;
@@ -61,7 +61,7 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         void clear()
-        { bzero(d, sizeof(d)); }
+        { std::memset(d, 0, sizeof(d)); }
     };
 }
 

src/arch/alpha/intregfile.hh

@@ -35,7 +35,7 @@
 #include "arch/alpha/types.hh"
 
 #include <iostream>
-#include <strings.h>
+#include <cstring>
 
 class Checkpoint;
 
@@ -71,7 +71,7 @@ namespace AlphaISA
         void unserialize(Checkpoint *cp, const std::string &section);
 
         void clear()
-        { bzero(regs, sizeof(regs)); }
+        { std::memset(regs, 0, sizeof(regs)); }
     };
 }
 

src/base/random.cc

@@ -37,6 +37,7 @@
 #include <cstdlib>
 #include <cmath>
 
+#include "base/fenv.hh"
 #include "base/random.hh"
 
 using namespace std;
@@ -59,7 +60,7 @@ m5round(double r)
 #if defined(__sun)
     double val;
     int oldrnd = m5_fegetround();
-    m5_fesetround(M5_FP_TONEAREST);
+    m5_fesetround(M5_FE_TONEAREST);
     val = rint(r);
     m5_fesetround(oldrnd);
     return val;

src/cpu/o3/lsq_unit.hh

@@ -33,6 +33,7 @@
 #define __CPU_O3_LSQ_UNIT_HH__
 
 #include <algorithm>
+#include <cstring>
 #include <map>
 #include <queue>
 
@@ -292,7 +293,7 @@ class LSQUnit {
             : inst(NULL), req(NULL), size(0),
               canWB(0), committed(0), completed(0)
         {
-            bzero(data, sizeof(data));
+            std::memset(data, 0, sizeof(data));
         }
 
         /** Constructs a store queue entry for a given instruction. */
@@ -300,7 +301,7 @@ class LSQUnit {
             : inst(_inst), req(NULL), size(0),
               canWB(0), committed(0), completed(0)
         {
-            bzero(data, sizeof(data));
+            std::memset(data, 0, sizeof(data));
         }
 
         /** The store instruction. */

src/dev/alpha/console.cc

@@ -76,7 +76,7 @@ AlphaConsole::AlphaConsole(Params *p)
     alphaAccess->diskOperation = 0;
     alphaAccess->outputChar = 0;
     alphaAccess->inputChar = 0;
-    bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
+    std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack));
 
 }