160 lines
6.5 KiB
C++
160 lines
6.5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#error "Cannot include this file"
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/**
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* The ExecContext is not a usable class. It is simply here for
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* documentation purposes. It shows the interface that is used by the
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* ISA to access and change CPU state.
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*/
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class ExecContext {
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to reduce overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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/** Reads an integer register. */
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uint64_t readIntRegOperand(const StaticInst *si, int idx);
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/** Reads a floating point register of a specific width. */
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FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
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/** Reads a floating point register of single register width. */
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FloatReg readFloatRegOperand(const StaticInst *si, int idx);
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/** Reads a floating point register of a specific width in its
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* binary format, instead of by value. */
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FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
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int width);
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/** Reads a floating point register in its binary format, instead
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* of by value. */
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FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
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/** Sets an integer register to a value. */
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void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
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/** Sets a floating point register of a specific width to a value. */
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void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
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int width);
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/** Sets a floating point register of single width to a value. */
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void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
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/** Sets the bits of a floating point register of a specific width
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* to a binary value. */
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val, int width);
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/** Sets the bits of a floating point register of single width
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* to a binary value. */
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val);
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/** Reads the PC. */
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uint64_t readPC();
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/** Reads the NextPC. */
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uint64_t readNextPC();
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/** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */
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uint64_t readNextNPC();
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/** Sets the PC. */
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void setPC(uint64_t val);
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/** Sets the NextPC. */
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void setNextPC(uint64_t val);
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/** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */
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void setNextNPC(uint64_t val);
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/** Reads a miscellaneous register. */
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MiscReg readMiscRegNoEffect(int misc_reg);
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/** Reads a miscellaneous register, handling any architectural
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* side effects due to reading that register. */
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MiscReg readMiscReg(int misc_reg);
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/** Sets a miscellaneous register. */
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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/** Sets a miscellaneous register, handling any architectural
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* side effects due to writing that register. */
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void setMiscReg(int misc_reg, const MiscReg &val);
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/** Records the effective address of the instruction. Only valid
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* for memory ops. */
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void setEA(Addr EA);
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/** Returns the effective address of the instruction. Only valid
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* for memory ops. */
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Addr getEA();
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/** Returns a pointer to the ThreadContext. */
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ThreadContext *tcBase();
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/** Reads an address, creating a memory request with the given
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* flags. Stores result of read in data. */
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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/** Writes to an address, creating a memory request with the given
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* flags. Writes data to memory. For store conditionals, returns
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* the result of the store in res. */
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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/** Prefetches an address, creating a memory request with the
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* given flags. */
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void prefetch(Addr addr, unsigned flags);
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/** Hints to the memory system that an address will be written to
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* soon, with the given size. Creates a memory request with the
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* given flags. */
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void writeHint(Addr addr, int size, unsigned flags);
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#if FULL_SYSTEM
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/** Somewhat Alpha-specific function that handles returning from
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* an error or interrupt. */
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Fault hwrei();
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/**
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* Check for special simulator handling of specific PAL calls. If
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* return value is false, actual PAL call will be suppressed.
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*/
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bool simPalCheck(int palFunc);
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#else
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/** Executes a syscall specified by the callnum. */
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void syscall(int64_t callnum);
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#endif
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};
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