Fix a couple LL/SC bugs that only affected timing mode.
src/cpu/simple/timing.cc: Fix swap/stq_c command bug. src/mem/packet.cc: Fix incorrect LoadLockedReq command response field. --HG-- extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
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2 changed files with 2 additions and 2 deletions
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@ -370,7 +370,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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}
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if (do_access) {
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dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
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dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
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dcache_pkt->allocate();
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dcache_pkt->set(data);
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@ -99,7 +99,7 @@ MemCmd::commandInfo[] =
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InvalidCmd, "ReadExResp" },
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/* LoadLockedReq */
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{ SET4(IsRead, IsLocked, IsRequest, NeedsResponse),
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ReadResp, "LoadLockedReq" },
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LoadLockedResp, "LoadLockedReq" },
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/* LoadLockedResp */
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{ SET4(IsRead, IsLocked, IsResponse, HasData),
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InvalidCmd, "LoadLockedResp" },
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