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gem5/src/cpu
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Miles Kaufmann 54cc0053f0 params: Deprecate old-style constructors; update most SimObject constructors. 
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-30 15:16:59 -04:00
..
checker Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
memtest params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
o3 params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
ozone Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
simple Merge with head 2007-08-26 21:45:40 -07:00
trace Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
activity.cc make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
activity.hh Update copyright. 2006-06-07 16:02:55 -04:00
base.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
base.hh Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
base_dyn_inst.hh O3 CPU: Remove alignment check from dynamic instruction read/write functions. 2007-08-26 20:31:30 -07:00
base_dyn_inst_impl.hh Fix compiler errors. 2007-06-20 19:46:45 -07:00
BaseCPU.py Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
cpu_models.py Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst. 2006-07-06 12:18:55 -04:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh Make SPARC checkpointing work 2007-01-30 18:25:39 -05:00
exec_context.hh *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
exetrace.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
exetrace.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
ExeTracer.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
FuncUnit.py Rename enum from OpType to OpClass so it's consistent with the 2007-06-11 23:10:58 -07:00
inst_seq.hh fixes so that M5 will compile under solaris 2006-11-04 21:41:01 -05:00
inteltrace.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
inteltrace.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
IntelTrace.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
intr_control.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
intr_control.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
legiontrace.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
LegionTrace.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc X86: Reorganize the native tracing code. 2007-08-01 12:01:51 -07:00
nativetrace.hh X86: Reorganize the native tracing code. 2007-08-01 12:01:51 -07:00
NativeTrace.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
op_class.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
pc_event.cc remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault 2007-03-12 17:23:08 -04:00
pc_event.hh Added sim/host.hh for the Addr type. 2006-11-07 05:42:15 -05:00
profile.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
profile.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
quiesce_event.cc Event descriptions should not end in "event" 2007-06-30 17:45:58 -07:00
quiesce_event.hh Update copyright. 2006-06-07 16:02:55 -04:00
SConscript Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
simple_thread.cc Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
simple_thread.hh Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
smt.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
static_inst.cc Modified instruction decode method. 2007-06-14 16:52:19 -04:00
static_inst.hh Port, StaticInst: Revert unnecessary changes. 2007-08-08 14:54:02 -04:00
thread_context.hh Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
thread_state.cc fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
thread_state.hh Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00