Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
This commit is contained in:
parent
cda354b070
commit
8dd7700482
|
@ -31,8 +31,12 @@ from m5.params import *
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from m5.proxy import *
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from m5 import build_env
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from Bus import Bus
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from InstTracer import InstTracer
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from ExeTracer import ExeTracer
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import sys
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default_tracer = ExeTracer()
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if build_env['FULL_SYSTEM']:
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if build_env['TARGET_ISA'] == 'alpha':
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from AlphaTLB import AlphaDTB, AlphaITB
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@ -83,6 +87,8 @@ class BaseCPU(SimObject):
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clock = Param.Clock('1t', "clock speed")
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phase = Param.Latency('0ns', "clock phase")
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tracer = Param.InstTracer(default_tracer, "Instruction tracer")
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_mem_ports = []
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def connectMemPorts(self, bus):
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36
src/cpu/ExeTracer.py
Normal file
36
src/cpu/ExeTracer.py
Normal file
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@ -0,0 +1,36 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class ExeTracer(InstTracer):
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type = 'ExeTracer'
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cxx_namespace = 'Trace'
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cxx_class = 'ExeTracer'
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36
src/cpu/IntelTrace.py
Normal file
36
src/cpu/IntelTrace.py
Normal file
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@ -0,0 +1,36 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class IntelTrace(InstTracer):
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type = 'IntelTrace'
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cxx_namespace = 'Trace'
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cxx_class = 'IntelTrace'
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36
src/cpu/LegionTrace.py
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36
src/cpu/LegionTrace.py
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@ -0,0 +1,36 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class LegionTrace(InstTracer):
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type = 'LegionTrace'
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cxx_namespace = 'Trace'
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cxx_class = 'LegionTrace'
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36
src/cpu/NativeTrace.py
Normal file
36
src/cpu/NativeTrace.py
Normal file
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@ -0,0 +1,36 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class NativeTrace(InstTracer):
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type = 'NativeTrace'
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cxx_namespace = 'Trace'
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cxx_class = 'NativeTrace'
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@ -105,12 +105,15 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
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SimObject('BaseCPU.py')
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SimObject('FuncUnit.py')
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SimObject('ExeTracer.py')
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SimObject('IntelTrace.py')
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Source('activity.cc')
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Source('base.cc')
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Source('cpuevent.cc')
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Source('exetrace.cc')
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Source('func_unit.cc')
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Source('inteltrace.cc')
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Source('pc_event.cc')
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Source('quiesce_event.cc')
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Source('static_inst.cc')
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@ -123,6 +126,14 @@ if env['FULL_SYSTEM']:
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Source('intr_control.cc')
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Source('profile.cc')
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if env['TARGET_ISA'] == 'sparc':
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SimObject('LegionTrace.py')
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Source('legiontrace.cc')
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if env['TARGET_ISA'] == 'x86':
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SimObject('NativeTrace.py')
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Source('nativetrace.cc')
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if env['USE_CHECKER']:
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Source('checker/cpu.cc')
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checker_supports = False
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@ -188,6 +188,7 @@ BaseCPU::BaseCPU(Params *p)
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if (params->profile)
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profileEvent = new ProfileEvent(this, params->profile);
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#endif
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tracer = params->tracer;
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}
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BaseCPU::Params::Params()
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profile = false;
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#endif
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checker = NULL;
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tracer = NULL;
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}
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void
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@ -38,6 +38,7 @@
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "sim/eventq.hh"
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#include "sim/insttracer.hh"
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#include "mem/mem_object.hh"
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#if FULL_SYSTEM
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@ -132,8 +133,13 @@ class BaseCPU : public MemObject
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std::vector<ThreadContext *> threadContexts;
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std::vector<TheISA::Predecoder *> predecoders;
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Trace::InstTracer * tracer;
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public:
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/// Provide access to the tracer pointer
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Trace::InstTracer * getTracer() { return tracer; }
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/// Notify the CPU that the indicated context is now active. The
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/// delay parameter indicates the number of ticks to wait before
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/// executing (typically 0 or 1).
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@ -169,6 +175,8 @@ class BaseCPU : public MemObject
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Tick functionTraceStart;
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System *system;
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int cpu_id;
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Trace::InstTracer * tracer;
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Tick phase;
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#if FULL_SYSTEM
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Tick profile;
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@ -31,772 +31,90 @@
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* Steve Raasch
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*/
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#include <errno.h>
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#include <fstream>
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#include <iomanip>
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#include <sys/ipc.h>
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#include <sys/shm.h>
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#include "arch/predecoder.hh"
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#include "arch/regfile.hh"
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#include "arch/utility.hh"
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#include "base/loader/symtab.hh"
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#include "base/socket.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "enums/OpClass.hh"
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#include "sim/system.hh"
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#if FULL_SYSTEM
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#include "arch/tlb.hh"
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#endif
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//XXX This is temporary
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#include "arch/isa_specific.hh"
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#include "cpu/m5legion_interface.h"
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#include "params/ExeTracer.hh"
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using namespace std;
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using namespace TheISA;
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#if THE_ISA == SPARC_ISA && FULL_SYSTEM
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static int diffcount = 0;
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static bool wasMicro = false;
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#endif
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namespace Trace {
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SharedData *shared_data = NULL;
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ListenSocket *cosim_listener = NULL;
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void
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setupSharedData()
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{
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int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
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if (shmfd < 0)
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fatal("Couldn't get shared memory fd. Is Legion running?");
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shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
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if (shared_data == (SharedData*)-1)
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fatal("Couldn't allocate shared memory");
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if (shared_data->flags != OWN_M5)
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fatal("Shared memory has invalid owner");
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if (shared_data->version != VERSION)
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fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
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shared_data->version);
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// step legion forward one cycle so we can get register values
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shared_data->flags = OWN_LEGION;
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Methods for the InstRecord object
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//
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#if THE_ISA == SPARC_ISA
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inline char * genCenteredLabel(int length, char * buffer, char * label)
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{
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int labelLength = strlen(label);
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assert(labelLength <= length);
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int leftPad = (length - labelLength) / 2;
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int rightPad = length - leftPad - labelLength;
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char format[64];
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sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
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sprintf(buffer, format, "", label, "");
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return buffer;
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}
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inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
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{
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ccprintf(os, " %16s | %#018x %s %#-018x \n",
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title, a, (a == b) ? "|" : "X", b);
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}
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inline void printColumnLabels(ostream & os)
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{
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static char * regLabel = genCenteredLabel(16, new char[17], "Register");
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static char * m5Label = genCenteredLabel(18, new char[18], "M5");
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static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
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ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel);
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ccprintf(os, "--------------------+-----------------------+-----------------------\n");
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}
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inline void printSectionHeader(ostream & os, char * name)
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{
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char sectionString[70];
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genCenteredLabel(69, sectionString, name);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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inline void printLevelHeader(ostream & os, int level)
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{
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char sectionString[70];
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char levelName[70];
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sprintf(levelName, "Trap stack level %d", level);
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genCenteredLabel(69, sectionString, levelName);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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#endif
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void
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Trace::InstRecord::dump()
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Trace::ExeTracerRecord::dump()
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{
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ostream &outs = Trace::output();
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DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
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bool diff = true;
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if (IsOn(ExecRegDelta))
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{
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diff = false;
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#ifndef NDEBUG
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#if THE_ISA == SPARC_ISA
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static int fd = 0;
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//Don't print what happens for each micro-op, just print out
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//once at the last op, and for regular instructions.
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if(!staticInst->isMicroop() || staticInst->isLastMicroop())
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{
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if(!cosim_listener)
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{
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int port = 8000;
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cosim_listener = new ListenSocket();
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while(!cosim_listener->listen(port, true))
|
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{
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DPRINTF(GDBMisc, "Can't bind port %d\n", port);
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port++;
|
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}
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ccprintf(cerr, "Listening for cosimulator on port %d\n", port);
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fd = cosim_listener->accept();
|
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}
|
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char prefix[] = "goli";
|
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for(int p = 0; p < 4; p++)
|
||||
{
|
||||
for(int i = 0; i < 8; i++)
|
||||
{
|
||||
uint64_t regVal;
|
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int res = read(fd, ®Val, sizeof(regVal));
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if(res < 0)
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panic("First read call failed! %s\n", strerror(errno));
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regVal = TheISA::gtoh(regVal);
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uint64_t realRegVal = thread->readIntReg(p * 8 + i);
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if((regVal & 0xffffffffULL) != (realRegVal & 0xffffffffULL))
|
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{
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DPRINTF(ExecRegDelta, "Register %s%d should be %#x but is %#x.\n", prefix[p], i, regVal, realRegVal);
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diff = true;
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}
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//ccprintf(outs, "%s%d m5 = %#x statetrace = %#x\n", prefix[p], i, realRegVal, regVal);
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}
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}
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/*for(int f = 0; f <= 62; f+=2)
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{
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uint64_t regVal;
|
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int res = read(fd, ®Val, sizeof(regVal));
|
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if(res < 0)
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panic("First read call failed! %s\n", strerror(errno));
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regVal = TheISA::gtoh(regVal);
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uint64_t realRegVal = thread->readFloatRegBits(f, 64);
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if(regVal != realRegVal)
|
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{
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DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
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}
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}*/
|
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uint64_t regVal;
|
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int res = read(fd, ®Val, sizeof(regVal));
|
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if(res < 0)
|
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panic("First read call failed! %s\n", strerror(errno));
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regVal = TheISA::gtoh(regVal);
|
||||
uint64_t realRegVal = thread->readNextPC();
|
||||
if(regVal != realRegVal)
|
||||
{
|
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DPRINTF(ExecRegDelta, "Register pc should be %#x but is %#x.\n", regVal, realRegVal);
|
||||
diff = true;
|
||||
}
|
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res = read(fd, ®Val, sizeof(regVal));
|
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if(res < 0)
|
||||
panic("First read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
realRegVal = thread->readNextNPC();
|
||||
if(regVal != realRegVal)
|
||||
{
|
||||
DPRINTF(ExecRegDelta, "Register npc should be %#x but is %#x.\n", regVal, realRegVal);
|
||||
diff = true;
|
||||
}
|
||||
res = read(fd, ®Val, sizeof(regVal));
|
||||
if(res < 0)
|
||||
panic("First read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
|
||||
if((regVal & 0xF) != (realRegVal & 0xF))
|
||||
{
|
||||
DPRINTF(ExecRegDelta, "Register ccr should be %#x but is %#x.\n", regVal, realRegVal);
|
||||
diff = true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#if 0 //THE_ISA == SPARC_ISA
|
||||
//Don't print what happens for each micro-op, just print out
|
||||
//once at the last op, and for regular instructions.
|
||||
if(!staticInst->isMicroop() || staticInst->isLastMicroop())
|
||||
{
|
||||
static uint64_t regs[32] = {
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0};
|
||||
static uint64_t ccr = 0;
|
||||
static uint64_t y = 0;
|
||||
static uint64_t floats[32];
|
||||
uint64_t newVal;
|
||||
static const char * prefixes[4] = {"G", "O", "L", "I"};
|
||||
if (IsOn(ExecTicks))
|
||||
ccprintf(outs, "%7d: ", when);
|
||||
|
||||
outs << hex;
|
||||
outs << "PC = " << thread->readNextPC();
|
||||
outs << " NPC = " << thread->readNextNPC();
|
||||
newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
|
||||
//newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR);
|
||||
if(newVal != ccr)
|
||||
{
|
||||
outs << " CCR = " << newVal;
|
||||
ccr = newVal;
|
||||
}
|
||||
newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1);
|
||||
//newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y);
|
||||
if(newVal != y)
|
||||
{
|
||||
outs << " Y = " << newVal;
|
||||
y = newVal;
|
||||
}
|
||||
for(int y = 0; y < 4; y++)
|
||||
{
|
||||
for(int x = 0; x < 8; x++)
|
||||
{
|
||||
int index = x + 8 * y;
|
||||
newVal = thread->readIntReg(index);
|
||||
if(regs[index] != newVal)
|
||||
{
|
||||
outs << " " << prefixes[y] << dec << x << " = " << hex << newVal;
|
||||
regs[index] = newVal;
|
||||
}
|
||||
}
|
||||
}
|
||||
for(int y = 0; y < 32; y++)
|
||||
{
|
||||
newVal = thread->readFloatRegBits(2 * y, 64);
|
||||
if(floats[y] != newVal)
|
||||
{
|
||||
outs << " F" << dec << (2 * y) << " = " << hex << newVal;
|
||||
floats[y] = newVal;
|
||||
}
|
||||
}
|
||||
outs << dec << endl;
|
||||
}
|
||||
#endif
|
||||
outs << thread->getCpuPtr()->name() << " ";
|
||||
|
||||
if (IsOn(ExecSpeculative))
|
||||
outs << (misspeculating ? "-" : "+") << " ";
|
||||
|
||||
if (IsOn(ExecThread))
|
||||
outs << "T" << thread->getThreadNum() << " : ";
|
||||
|
||||
|
||||
std::string sym_str;
|
||||
Addr sym_addr;
|
||||
if (debugSymbolTable
|
||||
&& IsOn(ExecSymbol)
|
||||
&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
|
||||
if (PC != sym_addr)
|
||||
sym_str += csprintf("+%d", PC - sym_addr);
|
||||
outs << "@" << sym_str << " : ";
|
||||
}
|
||||
if(!diff) {
|
||||
} else if (IsOn(ExecIntel)) {
|
||||
ccprintf(outs, "%7d ) ", when);
|
||||
outs << "0x" << hex << PC << ":\t";
|
||||
if (staticInst->isLoad()) {
|
||||
ccprintf(outs, "<RD %#x>", addr);
|
||||
} else if (staticInst->isStore()) {
|
||||
ccprintf(outs, "<WR %#x>", addr);
|
||||
}
|
||||
outs << endl;
|
||||
} else {
|
||||
if (IsOn(ExecTicks))
|
||||
ccprintf(outs, "%7d: ", when);
|
||||
|
||||
outs << thread->getCpuPtr()->name() << " ";
|
||||
|
||||
if (IsOn(ExecSpeculative))
|
||||
outs << (misspeculating ? "-" : "+") << " ";
|
||||
|
||||
if (IsOn(ExecThread))
|
||||
outs << "T" << thread->getThreadNum() << " : ";
|
||||
|
||||
|
||||
std::string sym_str;
|
||||
Addr sym_addr;
|
||||
if (debugSymbolTable
|
||||
&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
|
||||
&& IsOn(ExecSymbol)) {
|
||||
if (PC != sym_addr)
|
||||
sym_str += csprintf("+%d", PC - sym_addr);
|
||||
outs << "@" << sym_str << " : ";
|
||||
}
|
||||
else {
|
||||
outs << "0x" << hex << PC << " : ";
|
||||
}
|
||||
|
||||
//
|
||||
// Print decoded instruction
|
||||
//
|
||||
|
||||
#if defined(__GNUC__) && (__GNUC__ < 3)
|
||||
// There's a bug in gcc 2.x library that prevents setw()
|
||||
// from working properly on strings
|
||||
string mc(staticInst->disassemble(PC, debugSymbolTable));
|
||||
while (mc.length() < 26)
|
||||
mc += " ";
|
||||
outs << mc;
|
||||
#else
|
||||
outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
|
||||
#endif
|
||||
|
||||
outs << " : ";
|
||||
|
||||
if (IsOn(ExecOpClass)) {
|
||||
outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
|
||||
}
|
||||
|
||||
if (IsOn(ExecResult) && data_status != DataInvalid) {
|
||||
outs << " D=";
|
||||
#if 0
|
||||
if (data_status == DataDouble)
|
||||
ccprintf(outs, "%f", data.as_double);
|
||||
else
|
||||
ccprintf(outs, "%#018x", data.as_int);
|
||||
#else
|
||||
ccprintf(outs, "%#018x", data.as_int);
|
||||
#endif
|
||||
}
|
||||
|
||||
if (IsOn(ExecEffAddr) && addr_valid)
|
||||
outs << " A=0x" << hex << addr;
|
||||
|
||||
if (IsOn(ExecIntRegs) && regs_valid) {
|
||||
for (int i = 0; i < TheISA::NumIntRegs;)
|
||||
for (int j = i + 1; i <= j; i++)
|
||||
ccprintf(outs, "r%02d = %#018x%s", i,
|
||||
iregs->regs.readReg(i),
|
||||
((i == j) ? "\n" : " "));
|
||||
outs << "\n";
|
||||
}
|
||||
|
||||
if (IsOn(ExecFetchSeq) && fetch_seq_valid)
|
||||
outs << " FetchSeq=" << dec << fetch_seq;
|
||||
|
||||
if (IsOn(ExecCPSeq) && cp_seq_valid)
|
||||
outs << " CPSeq=" << dec << cp_seq;
|
||||
|
||||
//
|
||||
// End of line...
|
||||
//
|
||||
outs << endl;
|
||||
else {
|
||||
outs << "0x" << hex << PC << " : ";
|
||||
}
|
||||
#if THE_ISA == SPARC_ISA && FULL_SYSTEM
|
||||
static TheISA::Predecoder predecoder(NULL);
|
||||
// Compare
|
||||
if (IsOn(ExecLegion))
|
||||
{
|
||||
bool compared = false;
|
||||
bool diffPC = false;
|
||||
bool diffCC = false;
|
||||
bool diffInst = false;
|
||||
bool diffIntRegs = false;
|
||||
bool diffFpRegs = false;
|
||||
bool diffTpc = false;
|
||||
bool diffTnpc = false;
|
||||
bool diffTstate = false;
|
||||
bool diffTt = false;
|
||||
bool diffTba = false;
|
||||
bool diffHpstate = false;
|
||||
bool diffHtstate = false;
|
||||
bool diffHtba = false;
|
||||
bool diffPstate = false;
|
||||
bool diffY = false;
|
||||
bool diffFsr = false;
|
||||
bool diffCcr = false;
|
||||
bool diffTl = false;
|
||||
bool diffGl = false;
|
||||
bool diffAsi = false;
|
||||
bool diffPil = false;
|
||||
bool diffCwp = false;
|
||||
bool diffCansave = false;
|
||||
bool diffCanrestore = false;
|
||||
bool diffOtherwin = false;
|
||||
bool diffCleanwin = false;
|
||||
bool diffTlb = false;
|
||||
Addr m5Pc, lgnPc;
|
||||
|
||||
if (!shared_data)
|
||||
setupSharedData();
|
||||
//
|
||||
// Print decoded instruction
|
||||
//
|
||||
|
||||
// We took a trap on a micro-op...
|
||||
if (wasMicro && !staticInst->isMicroop())
|
||||
{
|
||||
// let's skip comparing this tick
|
||||
while (!compared)
|
||||
if (shared_data->flags == OWN_M5) {
|
||||
shared_data->flags = OWN_LEGION;
|
||||
compared = true;
|
||||
}
|
||||
compared = false;
|
||||
wasMicro = false;
|
||||
}
|
||||
outs << setw(26) << left;
|
||||
outs << staticInst->disassemble(PC, debugSymbolTable);
|
||||
outs << " : ";
|
||||
|
||||
if (staticInst->isLastMicroop())
|
||||
wasMicro = false;
|
||||
else if (staticInst->isMicroop())
|
||||
wasMicro = true;
|
||||
|
||||
|
||||
if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
|
||||
while (!compared) {
|
||||
if (shared_data->flags == OWN_M5) {
|
||||
m5Pc = PC & TheISA::PAddrImplMask;
|
||||
if (bits(shared_data->pstate,3,3)) {
|
||||
m5Pc &= mask(32);
|
||||
}
|
||||
lgnPc = shared_data->pc & TheISA::PAddrImplMask;
|
||||
if (lgnPc != m5Pc)
|
||||
diffPC = true;
|
||||
|
||||
if (shared_data->cycle_count !=
|
||||
thread->getCpuPtr()->instCount())
|
||||
diffCC = true;
|
||||
|
||||
if (shared_data->instruction !=
|
||||
(SparcISA::MachInst)staticInst->machInst) {
|
||||
diffInst = true;
|
||||
}
|
||||
// assume we have %g0 working correctly
|
||||
for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
|
||||
if (thread->readIntReg(i) != shared_data->intregs[i]) {
|
||||
diffIntRegs = true;
|
||||
}
|
||||
}
|
||||
for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
|
||||
if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
|
||||
diffFpRegs = true;
|
||||
}
|
||||
}
|
||||
uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL);
|
||||
if (oldTl != shared_data->tl)
|
||||
diffTl = true;
|
||||
for (int i = 1; i <= MaxTL; i++) {
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, i);
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
|
||||
shared_data->tpc[i-1])
|
||||
diffTpc = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
|
||||
shared_data->tnpc[i-1])
|
||||
diffTnpc = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
|
||||
shared_data->tstate[i-1])
|
||||
diffTstate = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TT) !=
|
||||
shared_data->tt[i-1])
|
||||
diffTt = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
|
||||
shared_data->htstate[i-1])
|
||||
diffHtstate = true;
|
||||
}
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
|
||||
|
||||
if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
|
||||
diffTba = true;
|
||||
//When the hpstate register is read by an instruction,
|
||||
//legion has bit 11 set. When it's in storage, it doesn't.
|
||||
//Since we don't directly support seperate interpretations
|
||||
//of the registers like that, the bit is always set to 1 and
|
||||
//we just don't compare it. It's not supposed to matter
|
||||
//anyway.
|
||||
if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE))
|
||||
diffHpstate = true;
|
||||
if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA))
|
||||
diffHtba = true;
|
||||
if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE))
|
||||
diffPstate = true;
|
||||
//if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y))
|
||||
if(shared_data->y !=
|
||||
thread->readIntReg(NumIntArchRegs + 1))
|
||||
diffY = true;
|
||||
if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) {
|
||||
diffFsr = true;
|
||||
if (mbits(shared_data->fsr, 63,10) ==
|
||||
mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) {
|
||||
thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr);
|
||||
diffFsr = false;
|
||||
}
|
||||
}
|
||||
//if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR))
|
||||
if(shared_data->ccr !=
|
||||
thread->readIntReg(NumIntArchRegs + 2))
|
||||
diffCcr = true;
|
||||
if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL))
|
||||
diffGl = true;
|
||||
if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI))
|
||||
diffAsi = true;
|
||||
if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL))
|
||||
diffPil = true;
|
||||
if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP))
|
||||
diffCwp = true;
|
||||
//if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE))
|
||||
if(shared_data->cansave !=
|
||||
thread->readIntReg(NumIntArchRegs + 3))
|
||||
diffCansave = true;
|
||||
//if(shared_data->canrestore !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
|
||||
if(shared_data->canrestore !=
|
||||
thread->readIntReg(NumIntArchRegs + 4))
|
||||
diffCanrestore = true;
|
||||
//if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
|
||||
if(shared_data->otherwin !=
|
||||
thread->readIntReg(NumIntArchRegs + 6))
|
||||
diffOtherwin = true;
|
||||
//if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
|
||||
if(shared_data->cleanwin !=
|
||||
thread->readIntReg(NumIntArchRegs + 5))
|
||||
diffCleanwin = true;
|
||||
|
||||
for (int i = 0; i < 64; i++) {
|
||||
if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i))
|
||||
diffTlb = true;
|
||||
if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i))
|
||||
diffTlb = true;
|
||||
}
|
||||
|
||||
if (diffPC || diffCC || diffInst || diffIntRegs ||
|
||||
diffFpRegs || diffTpc || diffTnpc || diffTstate ||
|
||||
diffTt || diffHpstate || diffHtstate || diffHtba ||
|
||||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
|
||||
diffGl || diffAsi || diffPil || diffCwp || diffCansave ||
|
||||
diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
|
||||
{
|
||||
|
||||
outs << "Differences found between M5 and Legion:";
|
||||
if (diffPC)
|
||||
outs << " [PC]";
|
||||
if (diffCC)
|
||||
outs << " [CC]";
|
||||
if (diffInst)
|
||||
outs << " [Instruction]";
|
||||
if (diffIntRegs)
|
||||
outs << " [IntRegs]";
|
||||
if (diffFpRegs)
|
||||
outs << " [FpRegs]";
|
||||
if (diffTpc)
|
||||
outs << " [Tpc]";
|
||||
if (diffTnpc)
|
||||
outs << " [Tnpc]";
|
||||
if (diffTstate)
|
||||
outs << " [Tstate]";
|
||||
if (diffTt)
|
||||
outs << " [Tt]";
|
||||
if (diffHpstate)
|
||||
outs << " [Hpstate]";
|
||||
if (diffHtstate)
|
||||
outs << " [Htstate]";
|
||||
if (diffHtba)
|
||||
outs << " [Htba]";
|
||||
if (diffPstate)
|
||||
outs << " [Pstate]";
|
||||
if (diffY)
|
||||
outs << " [Y]";
|
||||
if (diffFsr)
|
||||
outs << " [FSR]";
|
||||
if (diffCcr)
|
||||
outs << " [Ccr]";
|
||||
if (diffTl)
|
||||
outs << " [Tl]";
|
||||
if (diffGl)
|
||||
outs << " [Gl]";
|
||||
if (diffAsi)
|
||||
outs << " [Asi]";
|
||||
if (diffPil)
|
||||
outs << " [Pil]";
|
||||
if (diffCwp)
|
||||
outs << " [Cwp]";
|
||||
if (diffCansave)
|
||||
outs << " [Cansave]";
|
||||
if (diffCanrestore)
|
||||
outs << " [Canrestore]";
|
||||
if (diffOtherwin)
|
||||
outs << " [Otherwin]";
|
||||
if (diffCleanwin)
|
||||
outs << " [Cleanwin]";
|
||||
if (diffTlb)
|
||||
outs << " [Tlb]";
|
||||
outs << endl << endl;
|
||||
|
||||
outs << right << setfill(' ') << setw(15)
|
||||
<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
|
||||
<< hex << m5Pc << endl;
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
|
||||
<< lgnPc << endl << endl;
|
||||
|
||||
outs << right << setfill(' ') << setw(15)
|
||||
<< "M5 CC: " << "0x"<< setw(16) << setfill('0')
|
||||
<< hex << thread->getCpuPtr()->instCount() << endl;
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex
|
||||
<< shared_data->cycle_count << endl << endl;
|
||||
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "M5 Inst: " << "0x"<< setw(8)
|
||||
<< setfill('0') << hex << staticInst->machInst
|
||||
<< staticInst->disassemble(m5Pc, debugSymbolTable)
|
||||
<< endl;
|
||||
|
||||
predecoder.setTC(thread);
|
||||
predecoder.moreBytes(m5Pc, m5Pc,
|
||||
shared_data->instruction);
|
||||
|
||||
assert(predecoder.extMachInstReady());
|
||||
|
||||
StaticInstPtr legionInst =
|
||||
StaticInst::decode(predecoder.getExtMachInst(), lgnPc);
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< " Legion Inst: "
|
||||
<< "0x" << setw(8) << setfill('0') << hex
|
||||
<< shared_data->instruction
|
||||
<< legionInst->disassemble(lgnPc, debugSymbolTable)
|
||||
<< endl << endl;
|
||||
|
||||
printSectionHeader(outs, "General State");
|
||||
printColumnLabels(outs);
|
||||
printRegPair(outs, "HPstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_HPSTATE),
|
||||
shared_data->hpstate | (1 << 11));
|
||||
printRegPair(outs, "Htba",
|
||||
thread->readMiscRegNoEffect(MISCREG_HTBA),
|
||||
shared_data->htba);
|
||||
printRegPair(outs, "Pstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_PSTATE),
|
||||
shared_data->pstate);
|
||||
printRegPair(outs, "Y",
|
||||
//thread->readMiscRegNoEffect(MISCREG_Y),
|
||||
thread->readIntReg(NumIntArchRegs + 1),
|
||||
shared_data->y);
|
||||
printRegPair(outs, "FSR",
|
||||
thread->readMiscRegNoEffect(MISCREG_FSR),
|
||||
shared_data->fsr);
|
||||
printRegPair(outs, "Ccr",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CCR),
|
||||
thread->readIntReg(NumIntArchRegs + 2),
|
||||
shared_data->ccr);
|
||||
printRegPair(outs, "Tl",
|
||||
thread->readMiscRegNoEffect(MISCREG_TL),
|
||||
shared_data->tl);
|
||||
printRegPair(outs, "Gl",
|
||||
thread->readMiscRegNoEffect(MISCREG_GL),
|
||||
shared_data->gl);
|
||||
printRegPair(outs, "Asi",
|
||||
thread->readMiscRegNoEffect(MISCREG_ASI),
|
||||
shared_data->asi);
|
||||
printRegPair(outs, "Pil",
|
||||
thread->readMiscRegNoEffect(MISCREG_PIL),
|
||||
shared_data->pil);
|
||||
printRegPair(outs, "Cwp",
|
||||
thread->readMiscRegNoEffect(MISCREG_CWP),
|
||||
shared_data->cwp);
|
||||
printRegPair(outs, "Cansave",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CANSAVE),
|
||||
thread->readIntReg(NumIntArchRegs + 3),
|
||||
shared_data->cansave);
|
||||
printRegPair(outs, "Canrestore",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
|
||||
thread->readIntReg(NumIntArchRegs + 4),
|
||||
shared_data->canrestore);
|
||||
printRegPair(outs, "Otherwin",
|
||||
//thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
|
||||
thread->readIntReg(NumIntArchRegs + 6),
|
||||
shared_data->otherwin);
|
||||
printRegPair(outs, "Cleanwin",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
|
||||
thread->readIntReg(NumIntArchRegs + 5),
|
||||
shared_data->cleanwin);
|
||||
outs << endl;
|
||||
for (int i = 1; i <= MaxTL; i++) {
|
||||
printLevelHeader(outs, i);
|
||||
printColumnLabels(outs);
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, i);
|
||||
printRegPair(outs, "Tpc",
|
||||
thread->readMiscRegNoEffect(MISCREG_TPC),
|
||||
shared_data->tpc[i-1]);
|
||||
printRegPair(outs, "Tnpc",
|
||||
thread->readMiscRegNoEffect(MISCREG_TNPC),
|
||||
shared_data->tnpc[i-1]);
|
||||
printRegPair(outs, "Tstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_TSTATE),
|
||||
shared_data->tstate[i-1]);
|
||||
printRegPair(outs, "Tt",
|
||||
thread->readMiscRegNoEffect(MISCREG_TT),
|
||||
shared_data->tt[i-1]);
|
||||
printRegPair(outs, "Htstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_HTSTATE),
|
||||
shared_data->htstate[i-1]);
|
||||
}
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
|
||||
outs << endl;
|
||||
|
||||
printSectionHeader(outs, "General Purpose Registers");
|
||||
static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
|
||||
for(int y = 0; y < 4; y++) {
|
||||
for(int x = 0; x < 8; x++) {
|
||||
char label[8];
|
||||
sprintf(label, "%s%d", regtypes[y], x);
|
||||
printRegPair(outs, label,
|
||||
thread->readIntReg(y*8+x),
|
||||
shared_data->intregs[y*8+x]);
|
||||
}
|
||||
}
|
||||
if (diffFpRegs) {
|
||||
for (int x = 0; x < 32; x++) {
|
||||
char label[8];
|
||||
sprintf(label, "%%f%d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth),
|
||||
shared_data->fpregs[x]);
|
||||
}
|
||||
}
|
||||
if (diffTlb) {
|
||||
printColumnLabels(outs);
|
||||
char label[8];
|
||||
for (int x = 0; x < 64; x++) {
|
||||
if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
|
||||
thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
|
||||
sprintf(label, "I-TLB:%02d", x);
|
||||
printRegPair(outs, label, thread->getITBPtr()->TteRead(x),
|
||||
shared_data->itb[x]);
|
||||
}
|
||||
}
|
||||
for (int x = 0; x < 64; x++) {
|
||||
if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
|
||||
thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
|
||||
sprintf(label, "D-TLB:%02d", x);
|
||||
printRegPair(outs, label, thread->getDTBPtr()->TteRead(x),
|
||||
shared_data->dtb[x]);
|
||||
}
|
||||
}
|
||||
thread->getITBPtr()->dumpAll();
|
||||
thread->getDTBPtr()->dumpAll();
|
||||
}
|
||||
|
||||
diffcount++;
|
||||
if (diffcount > 3)
|
||||
fatal("Differences found between Legion and M5\n");
|
||||
} else
|
||||
diffcount = 0;
|
||||
|
||||
compared = true;
|
||||
shared_data->flags = OWN_LEGION;
|
||||
}
|
||||
} // while
|
||||
} // if not microop
|
||||
if (IsOn(ExecOpClass)) {
|
||||
outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
|
||||
}
|
||||
#endif
|
||||
|
||||
if (IsOn(ExecResult) && data_status != DataInvalid) {
|
||||
ccprintf(outs, " D=%#018x", data.as_int);
|
||||
}
|
||||
|
||||
if (IsOn(ExecEffAddr) && addr_valid)
|
||||
outs << " A=0x" << hex << addr;
|
||||
|
||||
if (IsOn(ExecFetchSeq) && fetch_seq_valid)
|
||||
outs << " FetchSeq=" << dec << fetch_seq;
|
||||
|
||||
if (IsOn(ExecCPSeq) && cp_seq_valid)
|
||||
outs << " CPSeq=" << dec << cp_seq;
|
||||
|
||||
//
|
||||
// End of line...
|
||||
//
|
||||
outs << endl;
|
||||
}
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// ExeTracer Simulation Object
|
||||
//
|
||||
Trace::ExeTracer *
|
||||
ExeTracerParams::create()
|
||||
{
|
||||
return new Trace::ExeTracer(name);
|
||||
};
|
||||
|
|
|
@ -32,141 +32,52 @@
|
|||
#ifndef __EXETRACE_HH__
|
||||
#define __EXETRACE_HH__
|
||||
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
#include <vector>
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "cpu/inst_seq.hh" // for InstSeqNum
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class InstRecord
|
||||
class ExeTracerRecord : public InstRecord
|
||||
{
|
||||
protected:
|
||||
typedef TheISA::IntRegFile IntRegFile;
|
||||
|
||||
Tick when;
|
||||
|
||||
// The following fields are initialized by the constructor and
|
||||
// thus guaranteed to be valid.
|
||||
ThreadContext *thread;
|
||||
// need to make this ref-counted so it doesn't go away before we
|
||||
// dump the record
|
||||
StaticInstPtr staticInst;
|
||||
Addr PC;
|
||||
bool misspeculating;
|
||||
|
||||
// The remaining fields are only valid for particular instruction
|
||||
// types (e.g, addresses for memory ops) or when particular
|
||||
// options are enabled (e.g., tracing full register contents).
|
||||
// Each data field has an associated valid flag to indicate
|
||||
// whether the data field is valid.
|
||||
Addr addr;
|
||||
bool addr_valid;
|
||||
|
||||
union {
|
||||
uint64_t as_int;
|
||||
double as_double;
|
||||
} data;
|
||||
enum {
|
||||
DataInvalid = 0,
|
||||
DataInt8 = 1, // set to equal number of bytes
|
||||
DataInt16 = 2,
|
||||
DataInt32 = 4,
|
||||
DataInt64 = 8,
|
||||
DataDouble = 3
|
||||
} data_status;
|
||||
|
||||
InstSeqNum fetch_seq;
|
||||
bool fetch_seq_valid;
|
||||
|
||||
InstSeqNum cp_seq;
|
||||
bool cp_seq_valid;
|
||||
|
||||
struct iRegFile {
|
||||
IntRegFile regs;
|
||||
};
|
||||
iRegFile *iregs;
|
||||
bool regs_valid;
|
||||
|
||||
public:
|
||||
InstRecord(Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr &_staticInst,
|
||||
Addr _pc, bool spec)
|
||||
: when(_when), thread(_thread),
|
||||
staticInst(_staticInst), PC(_pc),
|
||||
misspeculating(spec)
|
||||
ExeTracerRecord(Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr &_staticInst, Addr _pc, bool spec)
|
||||
: InstRecord(_when, _thread, _staticInst, _pc, spec)
|
||||
{
|
||||
data_status = DataInvalid;
|
||||
addr_valid = false;
|
||||
regs_valid = false;
|
||||
|
||||
fetch_seq_valid = false;
|
||||
cp_seq_valid = false;
|
||||
}
|
||||
|
||||
~InstRecord() { }
|
||||
|
||||
void setAddr(Addr a) { addr = a; addr_valid = true; }
|
||||
|
||||
void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
|
||||
void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
|
||||
void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
|
||||
void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
|
||||
void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
|
||||
void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
|
||||
|
||||
void setData(int64_t d) { setData((uint64_t)d); }
|
||||
void setData(int32_t d) { setData((uint32_t)d); }
|
||||
void setData(int16_t d) { setData((uint16_t)d); }
|
||||
void setData(int8_t d) { setData((uint8_t)d); }
|
||||
|
||||
void setData(double d) { data.as_double = d; data_status = DataDouble; }
|
||||
|
||||
void setFetchSeq(InstSeqNum seq)
|
||||
{ fetch_seq = seq; fetch_seq_valid = true; }
|
||||
|
||||
void setCPSeq(InstSeqNum seq)
|
||||
{ cp_seq = seq; cp_seq_valid = true; }
|
||||
|
||||
void setRegs(const IntRegFile ®s);
|
||||
|
||||
void dump();
|
||||
};
|
||||
|
||||
|
||||
inline void
|
||||
InstRecord::setRegs(const IntRegFile ®s)
|
||||
class ExeTracer : public InstTracer
|
||||
{
|
||||
if (!iregs)
|
||||
iregs = new iRegFile;
|
||||
public:
|
||||
|
||||
std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile));
|
||||
regs_valid = true;
|
||||
}
|
||||
ExeTracer(const std::string & name) : InstTracer(name)
|
||||
{}
|
||||
|
||||
inline InstRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
|
||||
Addr pc)
|
||||
{
|
||||
if (!IsOn(ExecEnable))
|
||||
return NULL;
|
||||
InstRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc,
|
||||
const StaticInstPtr staticInst, Addr pc)
|
||||
{
|
||||
if (!IsOn(ExecEnable))
|
||||
return NULL;
|
||||
|
||||
if (!Trace::enabled)
|
||||
return NULL;
|
||||
if (!Trace::enabled)
|
||||
return NULL;
|
||||
|
||||
if (!IsOn(ExecSpeculative) && tc->misspeculating())
|
||||
return NULL;
|
||||
if (!IsOn(ExecSpeculative) && tc->misspeculating())
|
||||
return NULL;
|
||||
|
||||
return new InstRecord(when, tc, staticInst, pc, tc->misspeculating());
|
||||
}
|
||||
return new ExeTracerRecord(when, tc,
|
||||
staticInst, pc, tc->misspeculating());
|
||||
}
|
||||
};
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
|
|
70
src/cpu/inteltrace.cc
Normal file
70
src/cpu/inteltrace.cc
Normal file
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Lisa Hsu
|
||||
* Nathan Binkert
|
||||
* Steve Raasch
|
||||
*/
|
||||
|
||||
#include <iomanip>
|
||||
|
||||
#include "cpu/exetrace.hh"
|
||||
#include "cpu/inteltrace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "params/IntelTrace.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
namespace Trace {
|
||||
|
||||
void
|
||||
Trace::IntelTraceRecord::dump()
|
||||
{
|
||||
ostream &outs = Trace::output();
|
||||
ccprintf(outs, "%7d ) ", when);
|
||||
outs << "0x" << hex << PC << ":\t";
|
||||
if (staticInst->isLoad()) {
|
||||
ccprintf(outs, "<RD %#x>", addr);
|
||||
} else if (staticInst->isStore()) {
|
||||
ccprintf(outs, "<WR %#x>", addr);
|
||||
}
|
||||
outs << endl;
|
||||
}
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// ExeTracer Simulation Object
|
||||
//
|
||||
Trace::IntelTrace *
|
||||
IntelTraceParams::create()
|
||||
{
|
||||
return new Trace::IntelTrace(name);
|
||||
};
|
84
src/cpu/inteltrace.hh
Normal file
84
src/cpu/inteltrace.hh
Normal file
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __INTELTRACE_HH__
|
||||
#define __INTELTRACE_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class IntelTraceRecord : public InstRecord
|
||||
{
|
||||
public:
|
||||
IntelTraceRecord(Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr &_staticInst, Addr _pc, bool spec)
|
||||
: InstRecord(_when, _thread, _staticInst, _pc, spec)
|
||||
{
|
||||
}
|
||||
|
||||
void dump();
|
||||
};
|
||||
|
||||
class IntelTrace : public InstTracer
|
||||
{
|
||||
public:
|
||||
|
||||
IntelTrace(const std::string & name) : InstTracer(name)
|
||||
{}
|
||||
|
||||
IntelTraceRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc,
|
||||
const StaticInstPtr staticInst, Addr pc)
|
||||
{
|
||||
if (!IsOn(ExecEnable))
|
||||
return NULL;
|
||||
|
||||
if (!Trace::enabled)
|
||||
return NULL;
|
||||
|
||||
if (!IsOn(ExecSpeculative) && tc->misspeculating())
|
||||
return NULL;
|
||||
|
||||
return new IntelTraceRecord(when, tc,
|
||||
staticInst, pc, tc->misspeculating());
|
||||
}
|
||||
};
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
#endif // __EXETRACE_HH__
|
600
src/cpu/legiontrace.cc
Normal file
600
src/cpu/legiontrace.cc
Normal file
|
@ -0,0 +1,600 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Lisa Hsu
|
||||
* Nathan Binkert
|
||||
* Steve Raasch
|
||||
*/
|
||||
|
||||
#include "arch/isa_specific.hh"
|
||||
#if THE_ISA != SPARC_ISA
|
||||
#error Legion tracing only works with SPARC simulations!
|
||||
#endif
|
||||
|
||||
#include "config/full_system.hh"
|
||||
#if !FULL_SYSTEM
|
||||
#error Legion tracing only works in full system!
|
||||
#endif
|
||||
|
||||
#include <iomanip>
|
||||
#include <sys/ipc.h>
|
||||
#include <sys/shm.h>
|
||||
|
||||
#include "arch/sparc/predecoder.hh"
|
||||
#include "arch/sparc/regfile.hh"
|
||||
#include "arch/sparc/utility.hh"
|
||||
#include "base/socket.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/legiontrace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "params/LegionTrace.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
#if FULL_SYSTEM
|
||||
#include "arch/tlb.hh"
|
||||
#endif
|
||||
|
||||
//XXX This is temporary
|
||||
#include "cpu/m5legion_interface.h"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
static int diffcount = 0;
|
||||
static bool wasMicro = false;
|
||||
#endif
|
||||
|
||||
namespace Trace {
|
||||
SharedData *shared_data = NULL;
|
||||
|
||||
void
|
||||
setupSharedData()
|
||||
{
|
||||
int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
|
||||
if (shmfd < 0)
|
||||
fatal("Couldn't get shared memory fd. Is Legion running?");
|
||||
|
||||
shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
|
||||
if (shared_data == (SharedData*)-1)
|
||||
fatal("Couldn't allocate shared memory");
|
||||
|
||||
if (shared_data->flags != OWN_M5)
|
||||
fatal("Shared memory has invalid owner");
|
||||
|
||||
if (shared_data->version != VERSION)
|
||||
fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
|
||||
shared_data->version);
|
||||
|
||||
// step legion forward one cycle so we can get register values
|
||||
shared_data->flags = OWN_LEGION;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Utility methods for pretty printing a report about a difference
|
||||
//
|
||||
|
||||
inline char * genCenteredLabel(int length, char * buffer, char * label)
|
||||
{
|
||||
int labelLength = strlen(label);
|
||||
assert(labelLength <= length);
|
||||
int leftPad = (length - labelLength) / 2;
|
||||
int rightPad = length - leftPad - labelLength;
|
||||
char format[64];
|
||||
sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
|
||||
sprintf(buffer, format, "", label, "");
|
||||
return buffer;
|
||||
}
|
||||
|
||||
inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
|
||||
{
|
||||
ccprintf(os, " %16s | %#018x %s %#-018x \n",
|
||||
title, a, (a == b) ? "|" : "X", b);
|
||||
}
|
||||
|
||||
inline void printColumnLabels(ostream & os)
|
||||
{
|
||||
static char * regLabel = genCenteredLabel(16, new char[17], "Register");
|
||||
static char * m5Label = genCenteredLabel(18, new char[18], "M5");
|
||||
static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
|
||||
ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel);
|
||||
ccprintf(os, "--------------------+-----------------------+-----------------------\n");
|
||||
}
|
||||
|
||||
inline void printSectionHeader(ostream & os, char * name)
|
||||
{
|
||||
char sectionString[70];
|
||||
genCenteredLabel(69, sectionString, name);
|
||||
ccprintf(os, "====================================================================\n");
|
||||
ccprintf(os, "%69s\n", sectionString);
|
||||
ccprintf(os, "====================================================================\n");
|
||||
}
|
||||
|
||||
inline void printLevelHeader(ostream & os, int level)
|
||||
{
|
||||
char sectionString[70];
|
||||
char levelName[70];
|
||||
sprintf(levelName, "Trap stack level %d", level);
|
||||
genCenteredLabel(69, sectionString, levelName);
|
||||
ccprintf(os, "====================================================================\n");
|
||||
ccprintf(os, "%69s\n", sectionString);
|
||||
ccprintf(os, "====================================================================\n");
|
||||
}
|
||||
|
||||
void
|
||||
Trace::LegionTraceRecord::dump()
|
||||
{
|
||||
ostream &outs = Trace::output();
|
||||
|
||||
static TheISA::Predecoder predecoder(NULL);
|
||||
// Compare
|
||||
bool compared = false;
|
||||
bool diffPC = false;
|
||||
bool diffCC = false;
|
||||
bool diffInst = false;
|
||||
bool diffIntRegs = false;
|
||||
bool diffFpRegs = false;
|
||||
bool diffTpc = false;
|
||||
bool diffTnpc = false;
|
||||
bool diffTstate = false;
|
||||
bool diffTt = false;
|
||||
bool diffTba = false;
|
||||
bool diffHpstate = false;
|
||||
bool diffHtstate = false;
|
||||
bool diffHtba = false;
|
||||
bool diffPstate = false;
|
||||
bool diffY = false;
|
||||
bool diffFsr = false;
|
||||
bool diffCcr = false;
|
||||
bool diffTl = false;
|
||||
bool diffGl = false;
|
||||
bool diffAsi = false;
|
||||
bool diffPil = false;
|
||||
bool diffCwp = false;
|
||||
bool diffCansave = false;
|
||||
bool diffCanrestore = false;
|
||||
bool diffOtherwin = false;
|
||||
bool diffCleanwin = false;
|
||||
bool diffTlb = false;
|
||||
Addr m5Pc, lgnPc;
|
||||
|
||||
if (!shared_data)
|
||||
setupSharedData();
|
||||
|
||||
// We took a trap on a micro-op...
|
||||
if (wasMicro && !staticInst->isMicroop())
|
||||
{
|
||||
// let's skip comparing this tick
|
||||
while (!compared)
|
||||
if (shared_data->flags == OWN_M5) {
|
||||
shared_data->flags = OWN_LEGION;
|
||||
compared = true;
|
||||
}
|
||||
compared = false;
|
||||
wasMicro = false;
|
||||
}
|
||||
|
||||
if (staticInst->isLastMicroop())
|
||||
wasMicro = false;
|
||||
else if (staticInst->isMicroop())
|
||||
wasMicro = true;
|
||||
|
||||
|
||||
if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
|
||||
while (!compared) {
|
||||
if (shared_data->flags == OWN_M5) {
|
||||
m5Pc = PC & SparcISA::PAddrImplMask;
|
||||
if (bits(shared_data->pstate,3,3)) {
|
||||
m5Pc &= mask(32);
|
||||
}
|
||||
lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
|
||||
if (lgnPc != m5Pc)
|
||||
diffPC = true;
|
||||
|
||||
if (shared_data->cycle_count !=
|
||||
thread->getCpuPtr()->instCount())
|
||||
diffCC = true;
|
||||
|
||||
if (shared_data->instruction !=
|
||||
(SparcISA::MachInst)staticInst->machInst) {
|
||||
diffInst = true;
|
||||
}
|
||||
// assume we have %g0 working correctly
|
||||
for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
|
||||
if (thread->readIntReg(i) != shared_data->intregs[i]) {
|
||||
diffIntRegs = true;
|
||||
}
|
||||
}
|
||||
for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
|
||||
if (thread->readFloatRegBits(i*2,
|
||||
FloatRegFile::DoubleWidth) !=
|
||||
shared_data->fpregs[i]) {
|
||||
diffFpRegs = true;
|
||||
}
|
||||
}
|
||||
uint64_t oldTl =
|
||||
thread->readMiscRegNoEffect(MISCREG_TL);
|
||||
if (oldTl != shared_data->tl)
|
||||
diffTl = true;
|
||||
for (int i = 1; i <= MaxTL; i++) {
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, i);
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
|
||||
shared_data->tpc[i-1])
|
||||
diffTpc = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
|
||||
shared_data->tnpc[i-1])
|
||||
diffTnpc = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
|
||||
shared_data->tstate[i-1])
|
||||
diffTstate = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_TT) !=
|
||||
shared_data->tt[i-1])
|
||||
diffTt = true;
|
||||
if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
|
||||
shared_data->htstate[i-1])
|
||||
diffHtstate = true;
|
||||
}
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
|
||||
|
||||
if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
|
||||
diffTba = true;
|
||||
//When the hpstate register is read by an instruction,
|
||||
//legion has bit 11 set. When it's in storage, it doesn't.
|
||||
//Since we don't directly support seperate interpretations
|
||||
//of the registers like that, the bit is always set to 1 and
|
||||
//we just don't compare it. It's not supposed to matter
|
||||
//anyway.
|
||||
if((shared_data->hpstate | (1 << 11)) !=
|
||||
thread->readMiscRegNoEffect(MISCREG_HPSTATE))
|
||||
diffHpstate = true;
|
||||
if(shared_data->htba !=
|
||||
thread->readMiscRegNoEffect(MISCREG_HTBA))
|
||||
diffHtba = true;
|
||||
if(shared_data->pstate !=
|
||||
thread->readMiscRegNoEffect(MISCREG_PSTATE))
|
||||
diffPstate = true;
|
||||
//if(shared_data->y !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_Y))
|
||||
if(shared_data->y !=
|
||||
thread->readIntReg(NumIntArchRegs + 1))
|
||||
diffY = true;
|
||||
if(shared_data->fsr !=
|
||||
thread->readMiscRegNoEffect(MISCREG_FSR)) {
|
||||
diffFsr = true;
|
||||
if (mbits(shared_data->fsr, 63,10) ==
|
||||
mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
|
||||
63,10)) {
|
||||
thread->setMiscRegNoEffect(MISCREG_FSR,
|
||||
shared_data->fsr);
|
||||
diffFsr = false;
|
||||
}
|
||||
}
|
||||
//if(shared_data->ccr !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_CCR))
|
||||
if(shared_data->ccr !=
|
||||
thread->readIntReg(NumIntArchRegs + 2))
|
||||
diffCcr = true;
|
||||
if(shared_data->gl !=
|
||||
thread->readMiscRegNoEffect(MISCREG_GL))
|
||||
diffGl = true;
|
||||
if(shared_data->asi !=
|
||||
thread->readMiscRegNoEffect(MISCREG_ASI))
|
||||
diffAsi = true;
|
||||
if(shared_data->pil !=
|
||||
thread->readMiscRegNoEffect(MISCREG_PIL))
|
||||
diffPil = true;
|
||||
if(shared_data->cwp !=
|
||||
thread->readMiscRegNoEffect(MISCREG_CWP))
|
||||
diffCwp = true;
|
||||
//if(shared_data->cansave !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_CANSAVE))
|
||||
if(shared_data->cansave !=
|
||||
thread->readIntReg(NumIntArchRegs + 3))
|
||||
diffCansave = true;
|
||||
//if(shared_data->canrestore !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
|
||||
if(shared_data->canrestore !=
|
||||
thread->readIntReg(NumIntArchRegs + 4))
|
||||
diffCanrestore = true;
|
||||
//if(shared_data->otherwin !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
|
||||
if(shared_data->otherwin !=
|
||||
thread->readIntReg(NumIntArchRegs + 6))
|
||||
diffOtherwin = true;
|
||||
//if(shared_data->cleanwin !=
|
||||
// thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
|
||||
if(shared_data->cleanwin !=
|
||||
thread->readIntReg(NumIntArchRegs + 5))
|
||||
diffCleanwin = true;
|
||||
|
||||
for (int i = 0; i < 64; i++) {
|
||||
if (shared_data->itb[i] !=
|
||||
thread->getITBPtr()->TteRead(i))
|
||||
diffTlb = true;
|
||||
if (shared_data->dtb[i] !=
|
||||
thread->getDTBPtr()->TteRead(i))
|
||||
diffTlb = true;
|
||||
}
|
||||
|
||||
if (diffPC || diffCC || diffInst ||
|
||||
diffIntRegs || diffFpRegs ||
|
||||
diffTpc || diffTnpc || diffTstate || diffTt ||
|
||||
diffHpstate || diffHtstate || diffHtba ||
|
||||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
|
||||
diffGl || diffAsi || diffPil || diffCwp ||
|
||||
diffCansave || diffCanrestore ||
|
||||
diffOtherwin || diffCleanwin || diffTlb) {
|
||||
|
||||
outs << "Differences found between M5 and Legion:";
|
||||
if (diffPC)
|
||||
outs << " [PC]";
|
||||
if (diffCC)
|
||||
outs << " [CC]";
|
||||
if (diffInst)
|
||||
outs << " [Instruction]";
|
||||
if (diffIntRegs)
|
||||
outs << " [IntRegs]";
|
||||
if (diffFpRegs)
|
||||
outs << " [FpRegs]";
|
||||
if (diffTpc)
|
||||
outs << " [Tpc]";
|
||||
if (diffTnpc)
|
||||
outs << " [Tnpc]";
|
||||
if (diffTstate)
|
||||
outs << " [Tstate]";
|
||||
if (diffTt)
|
||||
outs << " [Tt]";
|
||||
if (diffHpstate)
|
||||
outs << " [Hpstate]";
|
||||
if (diffHtstate)
|
||||
outs << " [Htstate]";
|
||||
if (diffHtba)
|
||||
outs << " [Htba]";
|
||||
if (diffPstate)
|
||||
outs << " [Pstate]";
|
||||
if (diffY)
|
||||
outs << " [Y]";
|
||||
if (diffFsr)
|
||||
outs << " [FSR]";
|
||||
if (diffCcr)
|
||||
outs << " [Ccr]";
|
||||
if (diffTl)
|
||||
outs << " [Tl]";
|
||||
if (diffGl)
|
||||
outs << " [Gl]";
|
||||
if (diffAsi)
|
||||
outs << " [Asi]";
|
||||
if (diffPil)
|
||||
outs << " [Pil]";
|
||||
if (diffCwp)
|
||||
outs << " [Cwp]";
|
||||
if (diffCansave)
|
||||
outs << " [Cansave]";
|
||||
if (diffCanrestore)
|
||||
outs << " [Canrestore]";
|
||||
if (diffOtherwin)
|
||||
outs << " [Otherwin]";
|
||||
if (diffCleanwin)
|
||||
outs << " [Cleanwin]";
|
||||
if (diffTlb)
|
||||
outs << " [Tlb]";
|
||||
outs << endl << endl;
|
||||
|
||||
outs << right << setfill(' ') << setw(15)
|
||||
<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
|
||||
<< hex << m5Pc << endl;
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "Legion PC: " << "0x"
|
||||
<< setw(16) << setfill('0') << hex
|
||||
<< lgnPc << endl << endl;
|
||||
|
||||
outs << right << setfill(' ') << setw(15)
|
||||
<< "M5 CC: " << "0x"
|
||||
<< setw(16) << setfill('0') << hex
|
||||
<< thread->getCpuPtr()->instCount() << endl;
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "Legion CC: " << "0x"
|
||||
<< setw(16) << setfill('0') << hex
|
||||
<< shared_data->cycle_count << endl << endl;
|
||||
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< "M5 Inst: " << "0x"
|
||||
<< setw(8) << setfill('0') << hex
|
||||
<< staticInst->machInst
|
||||
<< staticInst->disassemble(m5Pc, debugSymbolTable)
|
||||
<< endl;
|
||||
|
||||
predecoder.setTC(thread);
|
||||
predecoder.moreBytes(m5Pc, m5Pc,
|
||||
shared_data->instruction);
|
||||
|
||||
assert(predecoder.extMachInstReady());
|
||||
|
||||
StaticInstPtr legionInst =
|
||||
StaticInst::decode(predecoder.getExtMachInst(), lgnPc);
|
||||
outs << setfill(' ') << setw(15)
|
||||
<< " Legion Inst: "
|
||||
<< "0x" << setw(8) << setfill('0') << hex
|
||||
<< shared_data->instruction
|
||||
<< legionInst->disassemble(lgnPc, debugSymbolTable)
|
||||
<< endl << endl;
|
||||
|
||||
printSectionHeader(outs, "General State");
|
||||
printColumnLabels(outs);
|
||||
printRegPair(outs, "HPstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_HPSTATE),
|
||||
shared_data->hpstate | (1 << 11));
|
||||
printRegPair(outs, "Htba",
|
||||
thread->readMiscRegNoEffect(MISCREG_HTBA),
|
||||
shared_data->htba);
|
||||
printRegPair(outs, "Pstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_PSTATE),
|
||||
shared_data->pstate);
|
||||
printRegPair(outs, "Y",
|
||||
//thread->readMiscRegNoEffect(MISCREG_Y),
|
||||
thread->readIntReg(NumIntArchRegs + 1),
|
||||
shared_data->y);
|
||||
printRegPair(outs, "FSR",
|
||||
thread->readMiscRegNoEffect(MISCREG_FSR),
|
||||
shared_data->fsr);
|
||||
printRegPair(outs, "Ccr",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CCR),
|
||||
thread->readIntReg(NumIntArchRegs + 2),
|
||||
shared_data->ccr);
|
||||
printRegPair(outs, "Tl",
|
||||
thread->readMiscRegNoEffect(MISCREG_TL),
|
||||
shared_data->tl);
|
||||
printRegPair(outs, "Gl",
|
||||
thread->readMiscRegNoEffect(MISCREG_GL),
|
||||
shared_data->gl);
|
||||
printRegPair(outs, "Asi",
|
||||
thread->readMiscRegNoEffect(MISCREG_ASI),
|
||||
shared_data->asi);
|
||||
printRegPair(outs, "Pil",
|
||||
thread->readMiscRegNoEffect(MISCREG_PIL),
|
||||
shared_data->pil);
|
||||
printRegPair(outs, "Cwp",
|
||||
thread->readMiscRegNoEffect(MISCREG_CWP),
|
||||
shared_data->cwp);
|
||||
printRegPair(outs, "Cansave",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CANSAVE),
|
||||
thread->readIntReg(NumIntArchRegs + 3),
|
||||
shared_data->cansave);
|
||||
printRegPair(outs, "Canrestore",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
|
||||
thread->readIntReg(NumIntArchRegs + 4),
|
||||
shared_data->canrestore);
|
||||
printRegPair(outs, "Otherwin",
|
||||
//thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
|
||||
thread->readIntReg(NumIntArchRegs + 6),
|
||||
shared_data->otherwin);
|
||||
printRegPair(outs, "Cleanwin",
|
||||
//thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
|
||||
thread->readIntReg(NumIntArchRegs + 5),
|
||||
shared_data->cleanwin);
|
||||
outs << endl;
|
||||
for (int i = 1; i <= MaxTL; i++) {
|
||||
printLevelHeader(outs, i);
|
||||
printColumnLabels(outs);
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, i);
|
||||
printRegPair(outs, "Tpc",
|
||||
thread->readMiscRegNoEffect(MISCREG_TPC),
|
||||
shared_data->tpc[i-1]);
|
||||
printRegPair(outs, "Tnpc",
|
||||
thread->readMiscRegNoEffect(MISCREG_TNPC),
|
||||
shared_data->tnpc[i-1]);
|
||||
printRegPair(outs, "Tstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_TSTATE),
|
||||
shared_data->tstate[i-1]);
|
||||
printRegPair(outs, "Tt",
|
||||
thread->readMiscRegNoEffect(MISCREG_TT),
|
||||
shared_data->tt[i-1]);
|
||||
printRegPair(outs, "Htstate",
|
||||
thread->readMiscRegNoEffect(MISCREG_HTSTATE),
|
||||
shared_data->htstate[i-1]);
|
||||
}
|
||||
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
|
||||
outs << endl;
|
||||
|
||||
printSectionHeader(outs, "General Purpose Registers");
|
||||
static const char * regtypes[4] =
|
||||
{"%g", "%o", "%l", "%i"};
|
||||
for(int y = 0; y < 4; y++) {
|
||||
for(int x = 0; x < 8; x++) {
|
||||
char label[8];
|
||||
sprintf(label, "%s%d", regtypes[y], x);
|
||||
printRegPair(outs, label,
|
||||
thread->readIntReg(y*8+x),
|
||||
shared_data->intregs[y*8+x]);
|
||||
}
|
||||
}
|
||||
if (diffFpRegs) {
|
||||
for (int x = 0; x < 32; x++) {
|
||||
char label[8];
|
||||
sprintf(label, "%%f%d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->readFloatRegBits(x*2,
|
||||
FloatRegFile::DoubleWidth),
|
||||
shared_data->fpregs[x]);
|
||||
}
|
||||
}
|
||||
if (diffTlb) {
|
||||
printColumnLabels(outs);
|
||||
char label[8];
|
||||
for (int x = 0; x < 64; x++) {
|
||||
if (shared_data->itb[x] !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF) ||
|
||||
thread->getITBPtr()->TteRead(x) !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF)) {
|
||||
sprintf(label, "I-TLB:%02d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->getITBPtr()->TteRead(x),
|
||||
shared_data->itb[x]);
|
||||
}
|
||||
}
|
||||
for (int x = 0; x < 64; x++) {
|
||||
if (shared_data->dtb[x] !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF) ||
|
||||
thread->getDTBPtr()->TteRead(x) !=
|
||||
ULL(0xFFFFFFFFFFFFFFFF)) {
|
||||
sprintf(label, "D-TLB:%02d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->getDTBPtr()->TteRead(x),
|
||||
shared_data->dtb[x]);
|
||||
}
|
||||
}
|
||||
thread->getITBPtr()->dumpAll();
|
||||
thread->getDTBPtr()->dumpAll();
|
||||
}
|
||||
|
||||
diffcount++;
|
||||
if (diffcount > 3)
|
||||
fatal("Differences found between Legion and M5\n");
|
||||
} else
|
||||
diffcount = 0;
|
||||
|
||||
compared = true;
|
||||
shared_data->flags = OWN_LEGION;
|
||||
}
|
||||
} // while
|
||||
} // if not microop
|
||||
}
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// ExeTracer Simulation Object
|
||||
//
|
||||
Trace::LegionTrace *
|
||||
LegionTraceParams::create()
|
||||
{
|
||||
return new Trace::LegionTrace(name);
|
||||
};
|
77
src/cpu/legiontrace.hh
Normal file
77
src/cpu/legiontrace.hh
Normal file
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __LEGIONTRACE_HH__
|
||||
#define __LEGIONTRACE_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class LegionTraceRecord : public InstRecord
|
||||
{
|
||||
public:
|
||||
LegionTraceRecord(Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr &_staticInst, Addr _pc, bool spec)
|
||||
: InstRecord(_when, _thread, _staticInst, _pc, spec)
|
||||
{
|
||||
}
|
||||
|
||||
void dump();
|
||||
};
|
||||
|
||||
class LegionTrace : public InstTracer
|
||||
{
|
||||
public:
|
||||
|
||||
LegionTrace(const std::string & name) : InstTracer(name)
|
||||
{}
|
||||
|
||||
LegionTraceRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc,
|
||||
const StaticInstPtr staticInst, Addr pc)
|
||||
{
|
||||
if (tc->misspeculating())
|
||||
return NULL;
|
||||
|
||||
return new LegionTraceRecord(when, tc,
|
||||
staticInst, pc, tc->misspeculating());
|
||||
}
|
||||
};
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
#endif // __LEGIONTRACE_HH__
|
188
src/cpu/nativetrace.cc
Normal file
188
src/cpu/nativetrace.cc
Normal file
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Lisa Hsu
|
||||
* Nathan Binkert
|
||||
* Steve Raasch
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include "arch/regfile.hh"
|
||||
#include "arch/utility.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "base/socket.hh"
|
||||
#include "cpu/nativetrace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "params/NativeTrace.hh"
|
||||
|
||||
//XXX This is temporary
|
||||
#include "arch/isa_specific.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
namespace Trace {
|
||||
|
||||
NativeTrace::NativeTrace(const std::string & _name) : InstTracer(_name)
|
||||
{
|
||||
int port = 8000;
|
||||
while(!native_listener.listen(port, true))
|
||||
{
|
||||
DPRINTF(GDBMisc, "Can't bind port %d\n", port);
|
||||
port++;
|
||||
}
|
||||
ccprintf(cerr, "Listening for native process on port %d\n", port);
|
||||
fd = native_listener.accept();
|
||||
}
|
||||
|
||||
bool
|
||||
NativeTraceRecord::checkIntReg(const char * regName, int index, int size)
|
||||
{
|
||||
uint64_t regVal;
|
||||
int res = read(parent->fd, ®Val, size);
|
||||
if(res < 0)
|
||||
panic("Read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
uint64_t realRegVal = thread->readIntReg(index);
|
||||
if(regVal != realRegVal)
|
||||
{
|
||||
DPRINTFN("Register %s should be %#x but is %#x.\n",
|
||||
regName, regVal, realRegVal);
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool NativeTraceRecord::checkPC(const char * regName, int size)
|
||||
{
|
||||
uint64_t regVal;
|
||||
int res = read(parent->fd, ®Val, size);
|
||||
if(res < 0)
|
||||
panic("Read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
uint64_t realRegVal = thread->readNextPC();
|
||||
if(regVal != realRegVal)
|
||||
{
|
||||
DPRINTFN("%s should be %#x but is %#x.\n",
|
||||
regName, regVal, realRegVal);
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
Trace::NativeTraceRecord::dump()
|
||||
{
|
||||
// ostream &outs = Trace::output();
|
||||
|
||||
//Don't print what happens for each micro-op, just print out
|
||||
//once at the last op, and for regular instructions.
|
||||
if(!staticInst->isMicroop() || staticInst->isLastMicroop())
|
||||
{
|
||||
checkIntReg("rax", INTREG_RAX, sizeof(uint64_t));
|
||||
checkIntReg("rbx", INTREG_RBX, sizeof(uint64_t));
|
||||
checkIntReg("rcx", INTREG_RCX, sizeof(uint64_t));
|
||||
checkIntReg("rdx", INTREG_RDX, sizeof(uint64_t));
|
||||
checkIntReg("rsp", INTREG_RSP, sizeof(uint64_t));
|
||||
checkIntReg("rbp", INTREG_RBP, sizeof(uint64_t));
|
||||
checkIntReg("rsi", INTREG_RSI, sizeof(uint64_t));
|
||||
checkIntReg("rdi", INTREG_RDI, sizeof(uint64_t));
|
||||
checkIntReg("r8", INTREG_R8, sizeof(uint64_t));
|
||||
checkIntReg("r9", INTREG_R9, sizeof(uint64_t));
|
||||
checkIntReg("r10", INTREG_R10, sizeof(uint64_t));
|
||||
checkIntReg("r11", INTREG_R11, sizeof(uint64_t));
|
||||
checkIntReg("r12", INTREG_R12, sizeof(uint64_t));
|
||||
checkIntReg("r13", INTREG_R13, sizeof(uint64_t));
|
||||
checkIntReg("r14", INTREG_R14, sizeof(uint64_t));
|
||||
checkIntReg("r15", INTREG_R15, sizeof(uint64_t));
|
||||
checkPC("rip", sizeof(uint64_t));
|
||||
#if THE_ISA == SPARC_ISA
|
||||
/*for(int f = 0; f <= 62; f+=2)
|
||||
{
|
||||
uint64_t regVal;
|
||||
int res = read(fd, ®Val, sizeof(regVal));
|
||||
if(res < 0)
|
||||
panic("First read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
uint64_t realRegVal = thread->readFloatRegBits(f, 64);
|
||||
if(regVal != realRegVal)
|
||||
{
|
||||
DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
|
||||
}
|
||||
}*/
|
||||
uint64_t regVal;
|
||||
int res = read(fd, ®Val, sizeof(regVal));
|
||||
if(res < 0)
|
||||
panic("First read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
uint64_t realRegVal = thread->readNextPC();
|
||||
if(regVal != realRegVal)
|
||||
{
|
||||
DPRINTF(ExecRegDelta,
|
||||
"Register pc should be %#x but is %#x.\n",
|
||||
regVal, realRegVal);
|
||||
}
|
||||
res = read(fd, ®Val, sizeof(regVal));
|
||||
if(res < 0)
|
||||
panic("First read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
realRegVal = thread->readNextNPC();
|
||||
if(regVal != realRegVal)
|
||||
{
|
||||
DPRINTF(ExecRegDelta,
|
||||
"Register npc should be %#x but is %#x.\n",
|
||||
regVal, realRegVal);
|
||||
}
|
||||
res = read(fd, ®Val, sizeof(regVal));
|
||||
if(res < 0)
|
||||
panic("First read call failed! %s\n", strerror(errno));
|
||||
regVal = TheISA::gtoh(regVal);
|
||||
realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
|
||||
if((regVal & 0xF) != (realRegVal & 0xF))
|
||||
{
|
||||
DPRINTF(ExecRegDelta,
|
||||
"Register ccr should be %#x but is %#x.\n",
|
||||
regVal, realRegVal);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// ExeTracer Simulation Object
|
||||
//
|
||||
Trace::NativeTrace *
|
||||
NativeTraceParams::create()
|
||||
{
|
||||
return new Trace::NativeTrace(name);
|
||||
};
|
96
src/cpu/nativetrace.hh
Normal file
96
src/cpu/nativetrace.hh
Normal file
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __NATIVETRACE_HH__
|
||||
#define __NATIVETRACE_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class NativeTrace;
|
||||
|
||||
class NativeTraceRecord : public InstRecord
|
||||
{
|
||||
protected:
|
||||
NativeTrace * parent;
|
||||
|
||||
bool
|
||||
checkIntReg(const char * regName, int index, int size);
|
||||
|
||||
bool
|
||||
checkPC(const char * regName, int size);
|
||||
|
||||
public:
|
||||
NativeTraceRecord(NativeTrace * _parent,
|
||||
Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr &_staticInst, Addr _pc, bool spec)
|
||||
: InstRecord(_when, _thread, _staticInst, _pc, spec), parent(_parent)
|
||||
{
|
||||
}
|
||||
|
||||
void dump();
|
||||
};
|
||||
|
||||
class NativeTrace : public InstTracer
|
||||
{
|
||||
protected:
|
||||
int fd;
|
||||
|
||||
ListenSocket native_listener;
|
||||
|
||||
public:
|
||||
|
||||
NativeTrace(const std::string & name);
|
||||
|
||||
NativeTraceRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc,
|
||||
const StaticInstPtr staticInst, Addr pc)
|
||||
{
|
||||
if (tc->misspeculating())
|
||||
return NULL;
|
||||
|
||||
return new NativeTraceRecord(this, when, tc,
|
||||
staticInst, pc, tc->misspeculating());
|
||||
}
|
||||
|
||||
friend class NativeTraceRecord;
|
||||
};
|
||||
|
||||
/* namespace Trace */ }
|
||||
|
||||
#endif // __EXETRACE_HH__
|
|
@ -1156,9 +1156,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
|
|||
|
||||
#if TRACING_ON
|
||||
instruction->traceData =
|
||||
Trace::getInstRecord(curTick, cpu->tcBase(tid),
|
||||
instruction->staticInst,
|
||||
instruction->readPC());
|
||||
cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
|
||||
instruction->staticInst, instruction->readPC());
|
||||
#else
|
||||
instruction->traceData = NULL;
|
||||
#endif
|
||||
|
|
|
@ -590,6 +590,7 @@ AtomicSimpleCPUParams::create()
|
|||
params->simulate_stalls = simulate_stalls;
|
||||
params->system = system;
|
||||
params->cpu_id = cpu_id;
|
||||
params->tracer = tracer;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
params->itb = itb;
|
||||
|
|
|
@ -417,7 +417,7 @@ BaseSimpleCPU::preExecute()
|
|||
if(curStaticInst)
|
||||
{
|
||||
#if TRACING_ON
|
||||
traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
|
||||
traceData = tracer->getInstRecord(curTick, tc, curStaticInst,
|
||||
thread->readPC());
|
||||
|
||||
DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
|
||||
|
|
|
@ -719,6 +719,7 @@ TimingSimpleCPUParams::create()
|
|||
params->functionTraceStart = function_trace_start;
|
||||
params->system = system;
|
||||
params->cpu_id = cpu_id;
|
||||
params->tracer = tracer;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
params->itb = itb;
|
||||
|
|
35
src/sim/InstTracer.py
Normal file
35
src/sim/InstTracer.py
Normal file
|
@ -0,0 +1,35 @@
|
|||
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Gabe Black
|
||||
|
||||
from m5.SimObject import SimObject
|
||||
from m5.params import *
|
||||
|
||||
class InstTracer(SimObject):
|
||||
type = 'InstTracer'
|
||||
cxx_namespace = 'Trace'
|
||||
abstract = True
|
|
@ -32,6 +32,7 @@ Import('*')
|
|||
|
||||
SimObject('Root.py')
|
||||
SimObject('System.py')
|
||||
SimObject('InstTracer.py')
|
||||
|
||||
Source('async.cc')
|
||||
Source('core.cc')
|
||||
|
|
146
src/sim/insttracer.hh
Normal file
146
src/sim/insttracer.hh
Normal file
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __INSTRECORD_HH__
|
||||
#define __INSTRECORD_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "cpu/inst_seq.hh" // for InstSeqNum
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class InstRecord
|
||||
{
|
||||
protected:
|
||||
Tick when;
|
||||
|
||||
// The following fields are initialized by the constructor and
|
||||
// thus guaranteed to be valid.
|
||||
ThreadContext *thread;
|
||||
// need to make this ref-counted so it doesn't go away before we
|
||||
// dump the record
|
||||
StaticInstPtr staticInst;
|
||||
Addr PC;
|
||||
bool misspeculating;
|
||||
|
||||
// The remaining fields are only valid for particular instruction
|
||||
// types (e.g, addresses for memory ops) or when particular
|
||||
// options are enabled (e.g., tracing full register contents).
|
||||
// Each data field has an associated valid flag to indicate
|
||||
// whether the data field is valid.
|
||||
Addr addr;
|
||||
bool addr_valid;
|
||||
|
||||
union {
|
||||
uint64_t as_int;
|
||||
double as_double;
|
||||
} data;
|
||||
enum {
|
||||
DataInvalid = 0,
|
||||
DataInt8 = 1, // set to equal number of bytes
|
||||
DataInt16 = 2,
|
||||
DataInt32 = 4,
|
||||
DataInt64 = 8,
|
||||
DataDouble = 3
|
||||
} data_status;
|
||||
|
||||
InstSeqNum fetch_seq;
|
||||
bool fetch_seq_valid;
|
||||
|
||||
InstSeqNum cp_seq;
|
||||
bool cp_seq_valid;
|
||||
|
||||
public:
|
||||
InstRecord(Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr &_staticInst,
|
||||
Addr _pc, bool spec)
|
||||
: when(_when), thread(_thread),
|
||||
staticInst(_staticInst), PC(_pc),
|
||||
misspeculating(spec)
|
||||
{
|
||||
data_status = DataInvalid;
|
||||
addr_valid = false;
|
||||
|
||||
fetch_seq_valid = false;
|
||||
cp_seq_valid = false;
|
||||
}
|
||||
|
||||
virtual ~InstRecord() { }
|
||||
|
||||
void setAddr(Addr a) { addr = a; addr_valid = true; }
|
||||
|
||||
void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
|
||||
void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
|
||||
void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
|
||||
void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
|
||||
void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
|
||||
void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
|
||||
|
||||
void setData(int64_t d) { setData((uint64_t)d); }
|
||||
void setData(int32_t d) { setData((uint32_t)d); }
|
||||
void setData(int16_t d) { setData((uint16_t)d); }
|
||||
void setData(int8_t d) { setData((uint8_t)d); }
|
||||
|
||||
void setData(double d) { data.as_double = d; data_status = DataDouble; }
|
||||
|
||||
void setFetchSeq(InstSeqNum seq)
|
||||
{ fetch_seq = seq; fetch_seq_valid = true; }
|
||||
|
||||
void setCPSeq(InstSeqNum seq)
|
||||
{ cp_seq = seq; cp_seq_valid = true; }
|
||||
|
||||
virtual void dump() = 0;
|
||||
};
|
||||
|
||||
class InstTracer : public SimObject
|
||||
{
|
||||
public:
|
||||
InstTracer(const std::string & name) : SimObject(name)
|
||||
{}
|
||||
|
||||
virtual ~InstTracer()
|
||||
{};
|
||||
|
||||
virtual InstRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc,
|
||||
const StaticInstPtr staticInst, Addr pc) = 0;
|
||||
};
|
||||
|
||||
|
||||
|
||||
}; // namespace Trace
|
||||
|
||||
#endif // __INSTRECORD_HH__
|
Loading…
Reference in a new issue