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I thought this code got deleted, but since it hasn't I've moved it to a place where it doesn't access freed memory.

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--HG--
extra : convert_revision : 4d9023f6193004a3e9cbeebd3721bccb50b2aab0
This commit is contained in:
Ali Saidi 2007-03-10 15:00:41 -05:00
parent dc4d47bad4
commit ef6dfc2983
1 changed files with 7 additions and 7 deletions
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14
src/cpu/simple/timing.cc
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@ -275,14 +275,14 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// memory system takes ownership of packet
dcache_pkt = NULL;
}
// This will need a new way to tell if it has a dcache attached.
if (req->isUncacheable())
recordEvent("Uncached Read");
} else {
delete req;
}
// This will need a new way to tell if it has a dcache attached.
if (req->isUncacheable())
recordEvent("Uncached Read");
return fault;
}
@ -381,13 +381,13 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_pkt = NULL;
}
}
// This will need a new way to tell if it's hooked up to a cache or not.
if (req->isUncacheable())
recordEvent("Uncached Write");
} else {
delete req;
}
// This will need a new way to tell if it's hooked up to a cache or not.
if (req->isUncacheable())
recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling
// changeStatus() and changing it to "bad addr write" or something.