Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b
This commit is contained in:
Gabe Black
commit
a006aa067a
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|
@ -35,7 +35,7 @@ echo "waiting for server..."
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netcat -c -l -p 8000
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echo -n "running surge client..."
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/bin/bash -c "cd /benchmarks/specsurge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000"
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/bin/bash -c "cd /benchmarks/surge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000"
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echo "done."
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echo -n "halting machine"
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|
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@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
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{
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AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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@ -35,7 +35,7 @@
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/types.hh"
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#include <string.h>
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#include <cstring>
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#include <iostream>
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class Checkpoint;
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@ -61,7 +61,7 @@ namespace AlphaISA
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void unserialize(Checkpoint *cp, const std::string §ion);
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void clear()
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{ bzero(d, sizeof(d)); }
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{ std::memset(d, 0, sizeof(d)); }
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};
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}
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|
|
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@ -35,7 +35,7 @@
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#include "arch/alpha/types.hh"
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#include <iostream>
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#include <strings.h>
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#include <cstring>
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class Checkpoint;
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@ -71,7 +71,7 @@ namespace AlphaISA
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void unserialize(Checkpoint *cp, const std::string §ion);
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void clear()
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{ bzero(regs, sizeof(regs)); }
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{ std::memset(regs, 0, sizeof(regs)); }
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};
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}
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|
|
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@ -192,10 +192,10 @@ output decoder {{
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}
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const int AlphaFP::alphaToC99RoundingMode[] = {
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FE_TOWARDZERO, // Chopped
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FE_DOWNWARD, // Minus_Infinity
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FE_TONEAREST, // Normal
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FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
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M5_FE_TOWARDZERO, // Chopped
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M5_FE_DOWNWARD, // Minus_Infinity
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M5_FE_TONEAREST, // Normal
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M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
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};
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const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
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@ -228,10 +228,10 @@ def template FloatingPointExecute {{
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if (roundingMode == Normal) {
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%(code)s;
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} else {
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fesetround(getC99RoundingMode(
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m5_fesetround(getC99RoundingMode(
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xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
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%(code)s;
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fesetround(FE_TONEAREST);
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m5_fesetround(M5_FE_TONEAREST);
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}
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#else
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if (roundingMode != Normal && !warnedOnRounding) {
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|
|
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|
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@ -109,37 +109,22 @@ def format FpBasic(code, *flags) {{
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fp_code = """
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Fsr |= bits(Fsr,4,0) << 5;
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Fsr = insertBits(Fsr,4,0,0);
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#if defined(__sun) || defined (__OpenBSD__)
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fp_rnd newrnd = FP_RN;
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int newrnd = M5_FE_TONEAREST;
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switch (Fsr<31:30>) {
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case 0: newrnd = FP_RN; break;
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case 1: newrnd = FP_RZ; break;
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case 2: newrnd = FP_RP; break;
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case 3: newrnd = FP_RM; break;
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case 0: newrnd = M5_FE_TONEAREST; break;
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case 1: newrnd = M5_FE_TOWARDZERO; break;
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case 2: newrnd = M5_FE_UPWARD; break;
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case 3: newrnd = M5_FE_DOWNWARD; break;
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}
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fp_rnd oldrnd = fpsetround(newrnd);
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#else
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int newrnd = FE_TONEAREST;
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switch (Fsr<31:30>) {
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case 0: newrnd = FE_TONEAREST; break;
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case 1: newrnd = FE_TOWARDZERO; break;
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case 2: newrnd = FE_UPWARD; break;
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case 3: newrnd = FE_DOWNWARD; break;
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}
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int oldrnd = fegetround();
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fesetround(newrnd);
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#endif
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int oldrnd = m5_fegetround();
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m5_fesetround(newrnd);
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"""
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fp_code += code
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fp_code += """
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#if defined(__sun) || defined (__OpenBSD__)
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fpsetround(oldrnd);
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#else
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fesetround(oldrnd);
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#endif
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m5_fesetround(oldrnd);
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"""
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fp_code = filterDoubles(fp_code)
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iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
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|
|
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|
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@ -53,22 +53,14 @@ output decoder {{
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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#include "mem/packet.hh"
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#if defined(linux) || defined(__APPLE__)
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#include <fenv.h>
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#endif
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#include "base/fenv.hh"
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#include <algorithm>
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using namespace SparcISA;
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}};
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output exec {{
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#if defined(linux) || defined(__APPLE__)
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#include <fenv.h>
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#endif
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#if defined(__sun) || defined (__OpenBSD__)
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#include <ieeefp.h>
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#endif
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#include "base/fenv.hh"
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#if FULL_SYSTEM
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#include "sim/pseudo_inst.hh"
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|
|
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|
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@ -57,6 +57,7 @@ Source('circlebuf.cc')
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Source('cprintf.cc')
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Source('crc.cc')
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Source('fast_alloc.cc')
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Source('fenv.c')
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Source('fifo_buffer.cc')
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Source('hostinfo.cc')
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Source('hybrid_pred.cc')
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|
|
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56
src/base/fenv.c
Normal file
56
src/base/fenv.c
Normal file
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|
@ -0,0 +1,56 @@
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|||
/*
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||||
* Copyright (c) 2007 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Ali Saidi
|
||||
*/
|
||||
|
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#include <assert.h>
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#include <stdlib.h>
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#include <fenv.h>
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|
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void m5_fesetround(int rm);
|
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int m5_fegetround();
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|
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static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD};
|
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|
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void m5_fesetround(int rm)
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{
|
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assert(rm > 0 && rm < 4);
|
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fesetround(m5_round_ops[rm]);
|
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}
|
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|
||||
int m5_fegetround()
|
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{
|
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int x;
|
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int rm = fegetround();
|
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for(x = 0; x < 4; x++)
|
||||
if (m5_round_ops[x] == rm)
|
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return x;
|
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abort();
|
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return 0;
|
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}
|
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|
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|
|
@ -33,20 +33,21 @@
|
|||
|
||||
#include "config/use_fenv.hh"
|
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|
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#define M5_FE_DOWNWARD 0
|
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#define M5_FE_TONEAREST 1
|
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#define M5_FE_TOWARDZERO 2
|
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#define M5_FE_UPWARD 3
|
||||
|
||||
#if USE_FENV
|
||||
|
||||
#include <fenv.h>
|
||||
|
||||
extern "C" {
|
||||
void m5_fesetround(int rm);
|
||||
int m5_fegetround();
|
||||
}
|
||||
#else
|
||||
|
||||
// Dummy definitions to allow code to compile w/o a real <fenv.h>.
|
||||
|
||||
#define FE_TONEAREST 0
|
||||
#define FE_DOWNWARD 0
|
||||
#define FE_UPWARD 0
|
||||
#define FE_TOWARDZERO 0
|
||||
|
||||
inline int fesetround(int rounding_mode) { return 0; }
|
||||
inline void m5_fesetround(int rm) { ; }
|
||||
inline int m5_fegetround() {return 0; }
|
||||
|
||||
#endif // USE_FENV
|
||||
|
||||
|
|
|
|||
|
|
@ -29,9 +29,6 @@
|
|||
* Ali Saidi
|
||||
*/
|
||||
|
||||
#if defined(__sun)
|
||||
#include <ieeefp.h>
|
||||
#endif
|
||||
#ifdef __SUNPRO_CC
|
||||
#include <stdlib.h>
|
||||
#include <math.h>
|
||||
|
|
@ -40,6 +37,7 @@
|
|||
#include <cstdlib>
|
||||
#include <cmath>
|
||||
|
||||
#include "base/fenv.hh"
|
||||
#include "base/random.hh"
|
||||
|
||||
using namespace std;
|
||||
|
|
@ -61,9 +59,10 @@ m5round(double r)
|
|||
{
|
||||
#if defined(__sun)
|
||||
double val;
|
||||
fp_rnd oldrnd = fpsetround(FP_RN);
|
||||
int oldrnd = m5_fegetround();
|
||||
m5_fesetround(M5_FE_TONEAREST);
|
||||
val = rint(r);
|
||||
fpsetround(oldrnd);
|
||||
m5_fesetround(oldrnd);
|
||||
return val;
|
||||
#else
|
||||
return round(r);
|
||||
|
|
|
|||
|
|
@ -384,25 +384,25 @@ FullO3CPU<Impl>::fullCPURegStats()
|
|||
.name(name() + ".cpi")
|
||||
.desc("CPI: Cycles Per Instruction")
|
||||
.precision(6);
|
||||
cpi = simTicks / committedInsts;
|
||||
cpi = numCycles / committedInsts;
|
||||
|
||||
totalCpi
|
||||
.name(name() + ".cpi_total")
|
||||
.desc("CPI: Total CPI of All Threads")
|
||||
.precision(6);
|
||||
totalCpi = simTicks / totalCommittedInsts;
|
||||
totalCpi = numCycles / totalCommittedInsts;
|
||||
|
||||
ipc
|
||||
.name(name() + ".ipc")
|
||||
.desc("IPC: Instructions Per Cycle")
|
||||
.precision(6);
|
||||
ipc = committedInsts / simTicks;
|
||||
ipc = committedInsts / numCycles;
|
||||
|
||||
totalIpc
|
||||
.name(name() + ".ipc_total")
|
||||
.desc("IPC: Total IPC of All Threads")
|
||||
.precision(6);
|
||||
totalIpc = totalCommittedInsts / simTicks;
|
||||
totalIpc = totalCommittedInsts / numCycles;
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#define __CPU_O3_LSQ_UNIT_HH__
|
||||
|
||||
#include <algorithm>
|
||||
#include <cstring>
|
||||
#include <map>
|
||||
#include <queue>
|
||||
|
||||
|
|
@ -292,7 +293,7 @@ class LSQUnit {
|
|||
: inst(NULL), req(NULL), size(0),
|
||||
canWB(0), committed(0), completed(0)
|
||||
{
|
||||
bzero(data, sizeof(data));
|
||||
std::memset(data, 0, sizeof(data));
|
||||
}
|
||||
|
||||
/** Constructs a store queue entry for a given instruction. */
|
||||
|
|
@ -300,7 +301,7 @@ class LSQUnit {
|
|||
: inst(_inst), req(NULL), size(0),
|
||||
canWB(0), committed(0), completed(0)
|
||||
{
|
||||
bzero(data, sizeof(data));
|
||||
std::memset(data, 0, sizeof(data));
|
||||
}
|
||||
|
||||
/** The store instruction. */
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ AlphaConsole::AlphaConsole(Params *p)
|
|||
alphaAccess->diskOperation = 0;
|
||||
alphaAccess->outputChar = 0;
|
||||
alphaAccess->inputChar = 0;
|
||||
bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
|
||||
std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack));
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -73,6 +73,7 @@ for cpu in cpus:
|
|||
L1(size = '32kB', assoc = 4))
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
cpu.connectMemPorts(system.toL2Bus)
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
# connect memory to membus
|
||||
system.physmem.port = system.membus.port
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ class MyCache(BaseCache):
|
|||
cpu = DerivO3CPU(cpu_id=0)
|
||||
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
|
||||
MyCache(size = '2MB'))
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
system = System(cpu = cpu,
|
||||
physmem = PhysicalMemory(),
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -72,6 +72,7 @@ for cpu in cpus:
|
|||
L1(size = '32kB', assoc = 4))
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
cpu.connectMemPorts(system.toL2Bus)
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
# connect memory to membus
|
||||
system.physmem.port = system.membus.port
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
|
|||
membus = Bus())
|
||||
system.physmem.port = system.membus.port
|
||||
system.cpu.connectMemPorts(system.membus)
|
||||
system.cpu.clock = '2GHz'
|
||||
|
||||
root = Root(system = system)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -72,6 +72,7 @@ for cpu in cpus:
|
|||
L1(size = '32kB', assoc = 4))
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
cpu.connectMemPorts(system.toL2Bus)
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
# connect memory to membus
|
||||
system.physmem.port = system.membus.port
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -44,5 +44,6 @@ system = System(cpu = cpu,
|
|||
membus = Bus())
|
||||
system.physmem.port = system.membus.port
|
||||
cpu.connectMemPorts(system.membus)
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(system = system)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 615 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 1663 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 2032 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 15105 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154056 # Number of bytes of host memory used
|
||||
host_seconds 0.37 # Real time elapsed on the host
|
||||
host_tick_rate 3572881 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 13 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 606 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 1858 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 2195 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 22780 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154084 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_tick_rate 14337041 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 138 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5623 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 1331134 # Number of ticks simulated
|
||||
sim_seconds 0.000004 # Number of seconds simulated
|
||||
sim_ticks 3543500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 862 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 30311
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 6315
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 27595 9103.96%
|
||||
1 1579 520.93%
|
||||
2 482 159.02%
|
||||
3 232 76.54%
|
||||
4 131 43.22%
|
||||
5 104 34.31%
|
||||
6 60 19.79%
|
||||
7 27 8.91%
|
||||
8 101 33.32%
|
||||
0 4255 6737.93%
|
||||
1 915 1448.93%
|
||||
2 408 646.08%
|
||||
3 162 256.53%
|
||||
4 140 221.69%
|
||||
5 91 144.10%
|
||||
6 121 191.61%
|
||||
7 102 161.52%
|
||||
8 121 191.61%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 1791 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 5623 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
|
||||
system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1891 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 527 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 1857 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 471 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 31219
|
||||
system.cpu.fetch.rateDist.samples 7088
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 28979 9282.49%
|
||||
1 197 63.10%
|
||||
2 198 63.42%
|
||||
3 167 53.49%
|
||||
4 197 63.10%
|
||||
5 187 59.90%
|
||||
6 222 71.11%
|
||||
7 122 39.08%
|
||||
8 950 304.30%
|
||||
0 4755 6708.52%
|
||||
1 197 277.93%
|
||||
2 177 249.72%
|
||||
3 163 229.97%
|
||||
4 234 330.14%
|
||||
5 170 239.84%
|
||||
6 198 279.35%
|
||||
7 114 160.84%
|
||||
8 1080 1523.70%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 430 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 328 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1280 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 430 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 1288 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 328 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1280 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1288 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1267 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 48 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1031 # Number of stores executed
|
||||
system.cpu.iew.EXEC:branches 1203 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 41 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 989 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 5354 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 8160 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 5598 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7767 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 4055 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 4153 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 2 0.02% # Type of FU issued
|
||||
IntAlu 5868 67.12% # Type of FU issued
|
||||
IntAlu 5713 66.97% # Type of FU issued
|
||||
IntMult 1 0.01% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2 0.02% # Type of FU issued
|
||||
|
|
@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 1809 20.69% # Type of FU issued
|
||||
MemWrite 1061 12.14% # Type of FU issued
|
||||
MemRead 1773 20.78% # Type of FU issued
|
||||
MemWrite 1040 12.19% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 1.15% # attempts to use FU when none available
|
||||
IntAlu 7 5.47% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 54 62.07% # attempts to use FU when none available
|
||||
MemWrite 32 36.78% # attempts to use FU when none available
|
||||
MemRead 78 60.94% # attempts to use FU when none available
|
||||
MemWrite 43 33.59% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 31219
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 7088
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 27042 8662.03%
|
||||
1 1845 590.99%
|
||||
2 1151 368.69%
|
||||
3 572 183.22%
|
||||
4 318 101.86%
|
||||
5 182 58.30%
|
||||
6 76 24.34%
|
||||
7 22 7.05%
|
||||
8 11 3.52%
|
||||
0 4068 5739.28%
|
||||
1 771 1087.75%
|
||||
2 763 1076.47%
|
||||
3 485 684.26%
|
||||
4 504 711.06%
|
||||
5 295 416.20%
|
||||
6 144 203.16%
|
||||
7 40 56.43%
|
||||
8 18 25.40%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles
|
||||
system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
|
|
@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
|
|||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 481 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 485 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -380,31 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 31219 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 7088 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -6,9 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 30 2007 13:12:55
|
||||
M5 started Fri Mar 30 13:13:02 2007
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:06 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1331134 because target called exit()
|
||||
Exiting @ tick 3543500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,51 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -56,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -65,6 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
|
|
@ -76,6 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -101,14 +59,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -48,61 +47,11 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 684709 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148256 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 650634 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 357156 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148180 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 171417285 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5642 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 5641 # Number of ticks simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2820500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5642 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 3 2006 17:10:27
|
||||
M5 started Fri Nov 3 17:10:43 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
|
||||
Exiting @ tick 5641 because target called exit()
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:08 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2820500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,51 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -56,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -65,6 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
workload=system.cpu.workload
|
||||
|
|
@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -224,14 +182,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -48,7 +47,8 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
|
|
@ -176,54 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 167195 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179768 # Number of bytes of host memory used
|
||||
host_inst_rate 215467 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153656 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 51710933 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 193088667 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5642 # Number of instructions simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1767066 # Number of ticks simulated
|
||||
sim_seconds 0.000005 # Number of seconds simulated
|
||||
sim_ticks 5135000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1626 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 165 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5366 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 277 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 441 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1767066 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5135000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5642 # Number of instructions executed
|
||||
system.cpu.num_refs 1792 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 3 2006 17:10:27
|
||||
M5 started Fri Nov 3 17:10:44 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Exiting @ tick 1767066 because target called exit()
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:09 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 5135000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 187 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 653 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 41 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 217 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 426 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 832 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 170 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 19984 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153584 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 6228839 # Simulator tick rate (ticks/s)
|
||||
global.BPredUnit.BTBHits 162 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 671 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 427 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 860 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 31252 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153592 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 21107113 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 8 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 701 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 382 # Number of stores inserted to the mem dependence unit.
|
||||
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 746028 # Number of ticks simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1619000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 396 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 52 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 29809
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 2977
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 28885 9690.03%
|
||||
1 239 80.18%
|
||||
2 325 109.03%
|
||||
3 129 43.28%
|
||||
4 78 26.17%
|
||||
5 53 17.78%
|
||||
6 29 9.73%
|
||||
7 19 6.37%
|
||||
8 52 17.44%
|
||||
0 2102 7060.80%
|
||||
1 212 712.13%
|
||||
2 297 997.65%
|
||||
3 114 382.94%
|
||||
4 83 278.80%
|
||||
5 58 194.83%
|
||||
6 30 100.77%
|
||||
7 22 73.90%
|
||||
8 59 198.19%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1536 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 312.537914 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 312.537914 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 565 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 7055.843750 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7158.016393 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 677361 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.169912 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 436639 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.107965 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 7089.086420 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6946.208333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 213 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 574216 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.275510 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 57 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 166709 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.023529 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 859 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7071.056497 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 682 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1251577 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.206054 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 177 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 603348 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.098952 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 859 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7071.056497 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 682 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1251577 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.206054 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 177 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 92 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 603348 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.098952 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 687 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 144 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 46.650284 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 682 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 687 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 23701 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 129 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4617 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 5228 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 877 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 297 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 4 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 832 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 760 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1674 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 131 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5310 # Number of instructions fetch has processed
|
||||
system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 860 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 736 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.027635 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 760 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 357 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.176371 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 30107
|
||||
system.cpu.fetch.rateDist.samples 3239
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 29196 9697.41%
|
||||
1 37 12.29%
|
||||
2 87 28.90%
|
||||
3 73 24.25%
|
||||
4 125 41.52%
|
||||
5 66 21.92%
|
||||
6 42 13.95%
|
||||
7 50 16.61%
|
||||
8 431 143.16%
|
||||
0 2309 7128.74%
|
||||
1 47 145.11%
|
||||
2 82 253.16%
|
||||
3 70 216.12%
|
||||
4 128 395.18%
|
||||
5 58 179.07%
|
||||
6 37 114.23%
|
||||
7 46 142.02%
|
||||
8 462 1426.37%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 760 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4979.783333 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4157.255435 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 520 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1195148 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.315789 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 240 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 764935 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.242105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 2.826087 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 760 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4979.783333 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 520 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1195148 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.315789 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 240 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 764935 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.242105 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 543 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 193 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 760 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4979.783333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 520 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1195148 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.315789 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 240 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 764935 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.242105 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 543 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 193 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 91.559894 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 520 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 543 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 715922 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 547 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 269 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.108081 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 940 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 340 # Number of stores executed
|
||||
system.cpu.iew.EXEC:branches 535 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 256 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 339 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1841 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3178 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.788702 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1857 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3126 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1452 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.105557 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3194 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 16588 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 701 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 1462 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 62 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 382 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4113 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 600 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 110 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3254 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 297 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 286 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 88 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.003200 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.003200 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3364 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 2398 71.28% # Type of FU issued
|
||||
IntAlu 2413 71.45% # Type of FU issued
|
||||
IntMult 1 0.03% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
|
|
@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 618 18.37% # Type of FU issued
|
||||
MemWrite 347 10.32% # Type of FU issued
|
||||
MemRead 617 18.27% # Type of FU issued
|
||||
MemWrite 346 10.25% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010107 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 2.94% # attempts to use FU when none available
|
||||
IntAlu 1 2.70% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 11 32.35% # attempts to use FU when none available
|
||||
MemWrite 22 64.71% # attempts to use FU when none available
|
||||
MemRead 14 37.84% # attempts to use FU when none available
|
||||
MemWrite 22 59.46% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 30107
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 3239
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 28628 9508.75%
|
||||
1 616 204.60%
|
||||
2 335 111.27%
|
||||
3 225 74.73%
|
||||
4 177 58.79%
|
||||
5 80 26.57%
|
||||
6 31 10.30%
|
||||
7 11 3.65%
|
||||
8 4 1.33%
|
||||
0 2006 6193.27%
|
||||
1 362 1117.63%
|
||||
2 258 796.54%
|
||||
3 236 728.62%
|
||||
4 193 595.86%
|
||||
5 111 342.70%
|
||||
6 53 163.63%
|
||||
7 14 43.22%
|
||||
8 6 18.52%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.111735 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3838 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3364 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1301 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 682 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4610.717472 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2315.289963 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1240283 # number of ReadReq miss cycles
|
||||
system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 622813 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
|
|
@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
|
|||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4610.717472 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1240283 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 622813 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4610.717472 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1240283 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 269 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 271 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 622813 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -380,30 +379,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 138.742329 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 30107 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 16613 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 3239 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 14 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 5311 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 5020 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4436 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3192 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 802 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 297 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 23 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1424 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 7061 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -6,9 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 30 2007 13:12:55
|
||||
M5 started Fri Mar 30 13:13:05 2007
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:10 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 746028 because target called exit()
|
||||
Exiting @ tick 1619000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,51 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -56,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -65,6 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
|
|
@ -76,6 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -101,14 +59,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -48,61 +47,11 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 480164 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147928 # Number of bytes of host memory used
|
||||
host_inst_rate 254768 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147764 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 437596 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 121316260 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2578 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 2577 # Number of ticks simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 1288500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2578 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 3 2006 17:10:27
|
||||
M5 started Fri Nov 3 17:10:50 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
|
||||
Exiting @ tick 2577 because target called exit()
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:10 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1288500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,51 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -56,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -65,6 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
workload=system.cpu.workload
|
||||
|
|
@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -224,14 +182,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -48,7 +47,8 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
|
|
@ -176,54 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 153015 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179088 # Number of bytes of host memory used
|
||||
host_inst_rate 125225 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153176 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 56749783 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 116347710 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2578 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 980012 # Number of ticks simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 2444000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3988.472727 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2988.472727 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 219366 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 164366 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3991.518519 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2991.518519 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 107771 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 80771 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3989.475610 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 327137 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 245137 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 627 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 82 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 245137 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 45.884153 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3986.705521 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2986.705521 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 649833 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 486833 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3986.705521 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 649833 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 486833 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2416 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 163 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 486833 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 76.367476 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2987.632653 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1986.632653 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 731970 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 486725 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2987.632653 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 731970 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 486725 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 245 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 486725 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 122.501625 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 980012 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2444000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2578 # Number of instructions executed
|
||||
system.cpu.num_refs 710 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 3 2006 17:10:27
|
||||
M5 started Fri Nov 3 17:10:51 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Exiting @ tick 980012 because target called exit()
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:11 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2444000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -183,7 +183,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -7,9 +7,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 30 2007 13:12:55
|
||||
M5 started Fri Mar 30 13:13:07 2007
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:11 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2095164 because target called exit()
|
||||
Exiting @ tick 4600500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,51 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -56,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -65,6 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
|
|
@ -93,14 +50,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -40,61 +38,11 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1281059 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147756 # Number of bytes of host memory used
|
||||
host_seconds 0.39 # Real time elapsed on the host
|
||||
host_tick_rate 1279755 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 689098 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147724 # Number of bytes of host memory used
|
||||
host_seconds 0.73 # Real time elapsed on the host
|
||||
host_tick_rate 344128671 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500000 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 499999 # Number of ticks simulated
|
||||
sim_seconds 0.000250 # Number of seconds simulated
|
||||
sim_ticks 249999500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 500000 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -7,8 +7,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 3 2006 17:10:27
|
||||
M5 started Fri Nov 3 17:10:57 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
|
||||
Exiting @ tick 499999 because a thread reached the max instruction count
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:12 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 249999500 because a thread reached the max instruction count
|
||||
|
|
|
|||
|
|
@ -1,51 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -56,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -65,6 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
workload=system.cpu.workload
|
||||
|
|
@ -216,14 +173,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -40,7 +38,8 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
|
|
@ -168,54 +167,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 542626 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 178896 # Number of bytes of host memory used
|
||||
host_seconds 0.92 # Real time elapsed on the host
|
||||
host_tick_rate 4319791 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 518674 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153108 # Number of bytes of host memory used
|
||||
host_seconds 0.96 # Real time elapsed on the host
|
||||
host_tick_rate 355827019 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500000 # Number of instructions simulated
|
||||
sim_seconds 0.000004 # Number of seconds simulated
|
||||
sim_ticks 3982316 # Number of ticks simulated
|
||||
sim_seconds 0.000343 # Number of seconds simulated
|
||||
sim_ticks 343161000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 454 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 499597 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 403 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499597 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 857 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3982316 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 343161000 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 500000 # Number of instructions executed
|
||||
system.cpu.num_refs 182203 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -7,8 +7,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 3 2006 17:10:27
|
||||
M5 started Fri Nov 3 17:10:58 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Exiting @ tick 3982316 because a thread reached the max instruction count
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:14 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 343161000 because a thread reached the max instruction count
|
||||
|
|
|
|||
|
|
@ -1,48 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -610,12 +569,3 @@ responder_set=false
|
|||
width=16
|
||||
port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -524,51 +521,3 @@ clock=2
|
|||
width=16
|
||||
responder_set=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 435124 # Number of bytes of host memory used
|
||||
host_seconds 28.46 # Real time elapsed on the host
|
||||
host_tick_rate 202211 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303680 # Number of bytes of host memory used
|
||||
host_seconds 32.50 # Real time elapsed on the host
|
||||
host_tick_rate 177110 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000006 # Number of seconds simulated
|
||||
sim_ticks 5755736 # Number of ticks simulated
|
||||
|
|
@ -887,15 +887,15 @@ system.l2c.ReadReq_mshr_misses 66414 # nu
|
|||
system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable
|
||||
system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
|
||||
system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles
|
||||
system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits
|
||||
system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses
|
||||
system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses
|
||||
system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable
|
||||
system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
|
||||
system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits 18299 # number of Writeback hits
|
||||
system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses
|
||||
system.l2c.Writeback_misses 68315 # number of Writeback misses
|
||||
system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses
|
||||
system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses
|
||||
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 1.277186 # Average number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 6 2007 20:30:01
|
||||
M5 started Tue Feb 6 21:04:07 2007
|
||||
M5 executing on vm1
|
||||
M5 compiled Apr 21 2007 21:50:58
|
||||
M5 started Sat Apr 21 21:51:15 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
|
||||
warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional
|
||||
warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional
|
||||
|
|
@ -15,4 +15,5 @@ warning: overwriting port funcmem.functional value cpu3.functional with cpu4.fun
|
|||
warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional
|
||||
warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional
|
||||
warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 5755736 because Maximum number of loads reached!
|
||||
|
|
|
|||
Loading…
Reference in a new issue