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gem5/src/cpu
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Korey Sewell b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 
you are squashing from the current instruction # causing the thread exit.

--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
2008-02-27 16:53:08 -05:00
..
checker TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
memtest Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
o3 Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 2008-02-27 16:53:08 -05:00
ozone TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
simple TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
trace Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
activity.cc make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
activity.hh Update copyright. 2006-06-07 16:02:55 -04:00
base.cc Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
base.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
base_dyn_inst.hh TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
base_dyn_inst_impl.hh Fix compiler errors. 2007-06-20 19:46:45 -07:00
BaseCPU.py Add base ARM code to M5 2008-02-05 23:44:13 -05:00
cpu_models.py Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst. 2006-07-06 12:18:55 -04:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh Make SPARC checkpointing work 2007-01-30 18:25:39 -05:00
exec_context.hh *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
exetrace.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
exetrace.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
ExeTracer.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
FuncUnit.py Rename enum from OpType to OpClass so it's consistent with the 2007-06-11 23:10:58 -07:00
inst_seq.hh fixes so that M5 will compile under solaris 2006-11-04 21:41:01 -05:00
inteltrace.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
inteltrace.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
IntelTrace.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
intr_control.cc Interrupts: Inline some code and remove duplication. 2007-11-08 10:46:41 -05:00
intr_control.hh Interrupts: Inline some code and remove duplication. 2007-11-08 10:46:41 -05:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc String constant const-ness changes to placate g++ 4.2. 2007-10-31 18:04:22 -07:00
legiontrace.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
LegionTrace.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm. 2007-09-04 23:39:57 -07:00
nativetrace.hh X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm. 2007-09-04 23:39:57 -07:00
NativeTrace.py Turn the instruction tracing code into pluggable sim objects. 2007-07-28 20:30:43 -07:00
op_class.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
pc_event.cc remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault 2007-03-12 17:23:08 -04:00
pc_event.hh Added sim/host.hh for the Addr type. 2006-11-07 05:42:15 -05:00
profile.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
profile.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
quiesce_event.cc Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
quiesce_event.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
SConscript CPU: Add function to explictly compare thread contexts after copying. 2007-11-08 10:46:41 -05:00
simple_thread.cc Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
simple_thread.hh TLB: Make a TLB base class and put a virtual demapPage function in it. 2008-02-26 23:38:51 -05:00
smt.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
static_inst.cc Modified instruction decode method. 2007-06-14 16:52:19 -04:00
static_inst.hh Add base ARM code to M5 2008-02-05 23:44:13 -05:00
thread_context.cc CPU: Add function to explictly compare thread contexts after copying. 2007-11-08 10:46:41 -05:00
thread_context.hh add MicroPC functions back to thread context 2007-11-15 20:35:31 -05:00
thread_state.cc fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
thread_state.hh Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00