Couple more minor bug fixes for FS timing mode.
src/cpu/simple/timing.cc: Fix another SC problem. src/mem/cache/cache_impl.hh: Forgot to call makeTimingResponse() on uncached timing responses. --HG-- extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
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2 changed files with 8 additions and 6 deletions
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@ -356,8 +356,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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MemCmd cmd = MemCmd::WriteReq; // default
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bool do_access = true; // flag to suppress cache access
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assert(dcache_pkt == NULL);
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if (req->isLocked()) {
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cmd = MemCmd::StoreCondReq;
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do_access = TheISA::handleLockedWrite(thread, req);
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@ -369,11 +367,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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}
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}
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if (do_access) {
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dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
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dcache_pkt->allocate();
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dcache_pkt->set(data);
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// Note: need to allocate dcache_pkt even if do_access is
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// false, as it's used unconditionally to call completeAcc().
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assert(dcache_pkt == NULL);
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dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
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dcache_pkt->allocate();
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dcache_pkt->set(data);
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if (do_access) {
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if (!dcachePort.sendTiming(dcache_pkt)) {
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_status = DcacheRetry;
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} else {
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1
src/mem/cache/cache_impl.hh
vendored
1
src/mem/cache/cache_impl.hh
vendored
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@ -698,6 +698,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
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if (pkt->isRead()) {
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target->pkt->setData(pkt->getPtr<uint8_t>());
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}
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target->pkt->makeTimingResponse();
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cpuSidePort->respond(target->pkt, time);
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}
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assert(!mshr->hasTargets());
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