X86: Make a microcode branch microop.
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
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4 changed files with 29 additions and 3 deletions
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@ -1464,6 +1464,25 @@ class MemOperand(Operand):
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def makeAccSize(self):
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return self.size
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class UPCOperand(Operand):
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def makeConstructor(self):
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return ''
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def makeRead(self):
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return '%s = xc->readMicroPC();\n' % self.base_name
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def makeWrite(self):
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return 'xc->setMicroPC(%s);\n' % self.base_name
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class NUPCOperand(Operand):
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def makeConstructor(self):
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return ''
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def makeRead(self):
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return '%s = xc->readNextMicroPC();\n' % self.base_name
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def makeWrite(self):
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return 'xc->setNextMicroPC(%s);\n' % self.base_name
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class NPCOperand(Operand):
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def makeConstructor(self):
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@ -453,7 +453,7 @@ let {{
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
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def defineMicroRegOpImm(mnemonic, code):
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def defineMicroRegOpImm(mnemonic, code, flagCode=""):
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Name = mnemonic
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name = mnemonic.lower()
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code = immPick + code
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@ -615,11 +615,12 @@ let {{
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''')
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defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
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defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;')
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defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
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defineMicroRegOpRd('Rdip', 'DestReg = RIP')
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defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
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defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
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defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8 + 0*psrc1);', \
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flagCode = genCCFlagBitsLogic)
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defineMicroRegOpImm('Sext', '''
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@ -104,7 +104,9 @@ def operands {{
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'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
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'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
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'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
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'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
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'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
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'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
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'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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}};
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@ -291,11 +291,15 @@ class BaseSimpleCPU : public BaseCPU
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}
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uint64_t readPC() { return thread->readPC(); }
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uint64_t readMicroPC() { return thread->readMicroPC(); }
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uint64_t readNextPC() { return thread->readNextPC(); }
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uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
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uint64_t readNextNPC() { return thread->readNextNPC(); }
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void setPC(uint64_t val) { thread->setPC(val); }
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void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
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void setNextPC(uint64_t val) { thread->setNextPC(val); }
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void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
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void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
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MiscReg readMiscRegNoEffect(int misc_reg)
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