581 commits

Author	SHA1	Message	Date
Andreas Hansson	4bd61abb51	Stats: Update with use of std::map for ordered iteration in Ruby ... This patch updates the stats to reflect the changes due to the use of std::map instead of the hash map order-dependent iteration in Ruby.	2012-04-12 08:35:56 -04:00
Brad Beckmann	697fd8987b	regress: ruby random tester and hammer stats updates	2012-04-06 16:16:24 -07:00
Brad Beckmann	f050ebe3a8	MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality	2012-04-06 13:47:06 -07:00
Andreas Hansson	b00949d88b	MEM: Enable multiple distributed generalized memories ... This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh	2012-04-06 13:46:31 -04:00
Nilay Vaish	390cfc7be9	Config: Change the way options are added ... I am not too happy with the way options are added in files se.py and fs.py currently. This patch moves all the options to the file Options.py, functions from which are called when required.	2012-03-28 11:01:53 -05:00
Ali Saidi	3c666083c6	ARM: Update stats for IT and conditional branch changes	2012-03-21 10:36:45 -05:00
Ali Saidi	470051345a	ARM: Update stats for CBNZ fix.	2012-03-09 15:33:07 -05:00
Ali Saidi	927bba9d60	ARM: Update stats for valgrind fix and replace config.inis which are out of date.	2012-03-09 09:59:29 -05:00
Geoffrey Blake	da0d67c3d6	CheckerCPU: Make some basic regression tests for CheckerCPU ... Adds regression tests for the CheckerCPU. ARM ISA support only at this point.	2012-03-09 09:59:28 -05:00
Ali Saidi	eaa994e7f6	cache: Allow main memory to be at disjoint address ranges.	2012-03-09 09:59:25 -05:00
Gabe Black	cda4c2d280	Fix the SPARC fs regression by adding a call to createInterruptController.	2012-03-08 02:10:03 -08:00
Andreas Hansson	75681d3c1b	Stats: Update stats for changeset 8868 ... Changeset 8868 slightly changes the statistics for the parser and bzip2 regressions for ARM o3-timing. This patch merely updates the statistics to reflect these changes.	2012-03-06 11:14:54 -05:00
Andreas Hansson	32eae8094d	CPU: Check that the interrupt controller is created when needed ... This patch adds a creation-time check to the CPU to ensure that the interrupt controller is created for the cases where it is needed, i.e. if the CPU is not being switched in later and not a checker CPU. The patch also adds the "createInterruptController" call to a number of the regression scripts.	2012-03-02 09:21:48 -05:00
Andreas Hansson	c0b9f324bf	Stats: Fix the realview regression stats after nvmem move ... This patch updates the realview regressions stats to reflect that nvmem moved in the object hierarchy and is now under system.realview.	2012-03-02 09:18:50 -05:00
Steve Reinhardt	13e14ba93c	EIO: update stats (mostly order change, some renames)	2012-02-29 01:51:39 -05:00
Andreas Hansson	ac91f90145	Script: Fix the scripts that use the num_cpus cache parameter ... This patch merely removes the use of the num_cpus cache parameter which no longer exists after the introduction of the masterIds. The affected scripts fail when trying to set the parameter. Note that this patch does not update the regression stats.	2012-02-14 12:11:18 -05:00
Ali Saidi	0d46708dc2	bp: fix up stats for changes to branch predictor	2012-02-13 12:30:30 -06:00
Andreas Hansson	5a9a743cfc	MEM: Introduce the master/slave port roles in the Python classes ... This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.	2012-02-13 06:43:09 -05:00
Ali Saidi	8cb4a2208d	tests: fix diff-out script for op/inst stat changes.	2012-02-12 18:35:59 -06:00
Ali Saidi	4f8d1a4cef	stats: update stats for insts/ops and master id changes	2012-02-12 16:07:43 -06:00
Dam Sunwoo	230540e655	mem: fix cache stats to use request ids correctly ... This patch fixes the cache stats to use the new request ids. Cache stats also display the requestor names in the vector subnames. Most cache stats now include "nozero" and "nonan" flags to reduce the amount of excessive cache stat dump. Also, simplified incMissCount()/incHitCount() functions.	2012-02-12 16:07:39 -06:00
Nilay Vaish	b7cf64398f	Regressions: Update stats due to change in MESI protocol	2012-02-12 13:22:04 -06:00
Nilay Vaish	26ca8b8747	Regressions: Update stats due to O3 CPU changes	2012-02-10 09:51:37 -06:00
Gabe Black	e88165a431	Merge with main repository.	2012-01-30 21:07:57 -08:00
Andreas Hansson	ade53def92	Ruby: Connect system port in Ruby network test ... This patch moves the connection of the system port to create_system in Ruby.py. Thereby it allows the failing Ruby test (and other Ruby systems) to run again.	2012-01-30 09:37:06 -05:00
Gabe Black	39f314cc15	Yet another merge with the main repository. ... --HG-- rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt	2012-01-29 03:27:15 -08:00
Nilay Vaish	f19b3f30b4	X86 Regressions: Update stats due to introduction of TSO	2012-01-28 19:09:17 -06:00
Gabe Black	57e07ac2d2	SE/FS: Make both SE and FS tests available all the time. ... --HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => 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=> tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : 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=> tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/test.py => tests/long/se/60.bzip2/test.py rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simerr => 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tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : 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rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py	2012-01-28 07:24:45 -08:00
Gabe Black	ec20ee2f7c	SE/FS: Make SE vs. FS mode a runtime parameter.	2012-01-28 07:24:34 -08:00
Gabe Black	c3d41a2def	Merge with the main repo. ... --HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh	2012-01-28 07:24:01 -08:00
Gabe Black	da2a4acc26	Merge yet again with the main repository.	2012-01-16 04:27:10 -08:00
Ali Saidi	a17dbdf883	stats: Update stats for final tick and memory bandwidth patches	2012-01-25 17:19:50 +00:00
Andreas Hansson	2208ea049f	MEM: Make the bus bridge unidirectional and fixed address range ... This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.	2012-01-17 12:55:09 -06:00
Andreas Hansson	f85286b3de	MEM: Add port proxies instead of non-structural ports ... Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh	2012-01-17 12:55:08 -06:00
Andreas Hansson	06c39a154c	Ruby: Change the access permissions for MOESI hammer ... Regression statistics update.	2012-01-17 12:55:07 -06:00
Ali Saidi	8c7936c40c	stats: undo parser change from initparam change	2012-01-16 22:37:05 -05:00
Nilay Vaish	d272bdb1bf	MOESI Hammer: Update regression test output	2012-01-10 17:28:49 -06:00
Nilay Vaish	a5a2b9ecbd	X86 Regressions: Update stats due to fence instruction	2012-01-10 09:59:01 -06:00
Ali Saidi	8d757038b5	stats: Update stats for ARM init param changes.	2012-01-09 18:08:20 -06:00
Gabe Black	ec936364b7	Merge with the main repository again.	2012-01-07 02:15:35 -08:00
Gabe Black	36a822f08e	Merge with main repository.	2012-01-07 02:10:34 -08:00
Brad Beckmann	cb6ea0492f	regress: updated hammer memtest and rubytest outputs ... --HG-- extra : rebase_source : b02ad38b477d87bf28f7677c985ec7fe9a7d4694	2011-12-01 11:54:30 -08:00
Ali Saidi	d1dd7a24db	imported patch ext/stats_updates.patch ... --HG-- extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba	2011-12-01 00:15:23 -08:00
Chander Sudanthi	61c14da751	O3: Remove hardcoded tgts_per_mshr in O3CPU.py. ... There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b	2011-12-01 00:15:22 -08:00
Ali Saidi	e436d187e7	SPARC: update SE stats for FP fix ... --HG-- extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85	2011-11-30 18:57:11 -05:00
Gabe Black	0e621fd136	SPARC: Update the FS stats for the recent FP fix. ... --HG-- extra : rebase_source : 643e3541507576e30d9cd4dec045e5b94532c342	2011-11-28 04:19:57 -05:00
Nilay Vaish	f171a29118	Regression: Update statistics for x86 long regression tests ... This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.	2011-11-17 22:53:56 -06:00
Nilay Vaish	472645d62a	Tests: Update stats due to addition of fence microop	2011-11-05 15:32:23 -05:00
Steve Reinhardt	c6dd122fee	tests: fix spurious scons "Error 1" messages ... Turns out these are due to diff reporting that files acutally differed via a non-zero exit code.	2011-10-22 16:52:07 -07:00
Gabe Black	020e923ba7	Configs: Use connectAllPorts to connect ports for simple-timing-ruby.	2011-10-08 23:24:34 -07:00
Ali Saidi	ae62d97158	MIPS: Fix regressions tests	2011-09-17 12:34:03 -04:00
Ali Saidi	28a2236ec1	O3: Update stats for new ordering fix.	2011-09-13 12:58:09 -04:00
Gabe Black	c5fd6f4fec	MIPS: Update MIPS stats for cleaned up operand checks.	2011-09-09 01:35:05 -07:00
Ali Saidi	ba265abbfd	ARM: Add some MP regressions and clean up the disk images and kernels a bit	2011-08-19 15:08:09 -05:00
Ali Saidi	999cd8aef5	StoreSet: Update stats for store-set clearing	2011-08-19 15:08:08 -05:00
Ali Saidi	f125ef22b9	O3: Update stats for LSQ changes.	2011-08-19 15:08:06 -05:00
Gabe Black	cbf7982081	X86: Add an X86_FS o3 regression.	2011-08-14 18:34:17 -07:00
Gabe Black	a81d4a8fcd	Stats: Small update to stats for change to x86 inst flags.	2011-08-13 23:03:21 -07:00
Gabe Black	6bbd74e2d9	SCons,tests: Tell scons about pc-o3-timing regressions.	2011-08-09 11:33:12 -07:00
Gabe Black	c3e7b57fe7	Stats: Update stats for the end of macroop O3 fix.	2011-08-09 11:31:48 -07:00
Gabe Black	8586a800b7	Stats: Update stats for the recent O3 interrupt change.	2011-08-09 03:37:45 -07:00
Nilay Vaish	821dfc1289	BuildEnv: Eliminate RUBY as build environment variable ... This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled.	2011-08-08 10:50:13 -05:00
Gabe Black	9c806fe65a	Stats: Update stats for the previous change.	2011-08-07 15:41:09 -07:00
Gabe Black	a1aaeac2f9	Stats: Update the stats after the uninitialized branch predictor variable fix.	2011-08-07 09:22:18 -07:00
Nilay Vaish	1b49c56679	Scons: Drop RUBY as compile time option. ... This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled.	2011-08-02 00:10:08 -05:00
Gabe Black	6308ca27ff	Stats: Update stats for the recent fix to fetch.	2011-07-30 23:23:01 -07:00
Korey Sewell	145deb7c88	inorder-fs: temp. regression removal ... remove this regression till the fix for the hwrei instruction is put in	2011-07-15 21:26:18 -04:00
Ali Saidi	09914cdf8f	ARM: Update stats for better miscreg support for MP configurations.	2011-07-15 11:53:35 -05:00
Ali Saidi	3ebfe2eb01	O3: Update stats for fetch and bp changes.	2011-07-10 12:56:09 -05:00
Gabe Black	a4bd05dc37	X86: Add a config for an FS regression on O3.	2011-07-05 17:46:46 -07:00
Gabe Black	d42e471baa	Stats: Update stats for the x86 store fault fix.	2011-07-02 22:31:42 -07:00
Brad Beckmann	12dc51ff0d	Regression: Updates regression outputs for Ruby memtest ... This patch updates the regression outputs for Ruby memtest. This was required because of the changes carried out by the addition of functional access support to Ruby.	2011-06-30 19:57:26 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)	c86f849d5a	Ruby: Add support for functional accesses ... This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.	2011-06-30 19:49:26 -05:00
Korey Sewell	6630d4c64b	inorder: sparc: add 02.insttest regression	2011-06-20 22:44:24 -04:00
Korey Sewell	d1e8be9a73	inorder: sparc: add hello world regression ... - add InOrderCPU compile option to SPARC - add hello regression for SPARC	2011-06-20 22:44:22 -04:00
Korey Sewell	08c1a6f41b	merge regression updates	2011-06-20 18:58:31 -04:00
Korey Sewell	b5736ba4ef	alpha:o3:simple: update simout/err files ... A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.	2011-06-20 18:57:14 -04:00
Korey Sewell	9124f46587	inorder: alpha-hello regression update	2011-06-20 12:21:10 -04:00
Korey Sewell	97449ef3da	inorder: update eon regr w/eon info ... previous commit copied over O3 stats, this one puts the inorder ones in the right place	2011-06-19 21:54:53 -04:00
Korey Sewell	d16b0dc319	inorder: add 10.linux-boot regression	2011-06-19 21:43:43 -04:00
Korey Sewell	60da569846	inorder: add eon regression	2011-06-19 21:43:43 -04:00
Korey Sewell	55dce6419d	inorder: update SE regressions	2011-06-19 21:43:42 -04:00
Korey Sewell	e8b7df072b	inorder: make InOrder CPU FS compilable/visible ... make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile	2011-06-19 21:43:39 -04:00
Korey Sewell	1aa4869ff0	sparc: update long regressions	2011-06-12 21:35:03 -04:00
Korey Sewell	fb8c958241	sparc: update o3 regressions	2011-06-10 22:15:34 -04:00
Korey Sewell	9331b5d26a	sparc: update simple cpu regressions ... use stats file generated by zizzer	2011-06-10 03:45:24 -04:00
Steve Reinhardt	8a652f9871	config: tweak ruby configs to clean up hierarchy ... Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first.	2011-05-23 14:29:23 -07:00
Ali Saidi	5d5b0f49cc	Stats: Update stats for minor O3 changes below.	2011-05-23 10:59:13 -05:00
Ali Saidi	44e599a1a4	ARM: Fix up stats for previous changes to condition codes	2011-05-13 17:29:27 -05:00
Ali Saidi	fea2c26402	ARM: Update ARM_FS stats for mp changes	2011-05-04 20:38:28 -05:00
Ali Saidi	307f089e7f	O3/ARM: Update stats for recent changes.	2011-05-04 20:38:27 -05:00
Brad Beckmann	001c16bc6d	regress: updates after changing ruby network bandwidth	2011-04-28 17:18:16 -07:00
Nathan Binkert	3d93439ee0	stats: update 20.parser o3 now that it works. realview-o3 works too.	2011-04-25 14:18:08 -07:00
Nathan Binkert	a7e27f9a82	tests: updates for stat name change	2011-04-22 10:18:51 -07:00
Nathan Binkert	8c1563096c	tests: update stats for name changes	2011-04-19 18:45:23 -07:00
Ali Saidi	d50d0152d0	ARM: Fix stats for ARM_SE checkpoint restore fix. ... Register reads/writes done in startup() count against the stats while they don't count if done in initState().	2011-04-12 16:09:20 -04:00
Ali Saidi	afa897403d	ARM: Update stats for default inclusion of CF adapter.	2011-04-04 11:42:32 -05:00
Ali Saidi	b20e92e1ca	ARM: Update stats for previous changes.	2011-04-04 11:42:31 -05:00
Ali Saidi	1114be4b78	O3: Update stats for memory order violation checking patch.	2011-04-04 11:42:25 -05:00
Steve Reinhardt	bb67c706d6	tests: update reference outputs for ruby cache index change ... MOESI_CMP_token is the only protocol that showed noticeable stats differences.	2011-03-26 22:24:36 -07:00
Ali Saidi	63eb337b3b	ARM: Update stats for the previous changes and add ARM_FS/O3 regression.	2011-03-17 19:20:22 -05:00
Ali Saidi	845f791f37	Stats: Update the statistics for rfe patch.	2011-03-17 19:20:20 -05:00
Ali Saidi	7112b44362	O3: Update regressions for mem block caching change.	2011-03-17 19:20:19 -05:00
Ali Saidi	a432d8e085	Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. ... This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.	2011-03-17 19:20:19 -05:00
Ali Saidi	3a44307e94	X86: Update the stats for parser on x86 O3.	2011-03-17 00:43:54 -04:00
Gabe Black	27f5a8c812	X86: Update the stats for gzip on x86 O3.	2011-03-16 19:08:41 -07:00
Gabe Black	47615d06bd	Regressions: Move the X86_FS regressions to "quick" instead of "long". ... --HG-- rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal	2011-03-12 14:41:30 -08:00
Gabe Black	fa448129b1	SCons: Turn some scons variables into command line options.	2011-03-03 23:54:31 -08:00
Gabe Black	e8b982e247	X86: Update stats for the x86 o3 hello world regression.	2011-03-01 23:18:00 -08:00
Gabe Black	b84ae9bd40	X86: Update X86_FS stats.	2011-02-27 16:24:54 -08:00
Korey Sewell	8135b81ae4	inorder: bzip2 regression update	2011-02-27 14:17:26 -05:00
Brad Beckmann	ae52ff631f	regress: MOESI_hammer memtest updates	2011-02-23 16:41:59 -08:00
Korey Sewell	72fb282ab1	inorder: add 00.gzip and 60.bzip2 regression tests	2011-02-23 16:35:25 -05:00
Ali Saidi	73603c2b17	ARM: Update regression tests for preceeding changes.	2011-02-23 15:10:50 -06:00
Ali Saidi	79dac89552	ARM: Clarifies creation of Linux and baremetal ARM systems. ... makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.	2011-02-23 15:10:48 -06:00
Korey Sewell	66bb732c04	m5: merge inorder/release-notes/make_release changes	2011-02-18 14:35:15 -05:00
Korey Sewell	ab9c20cc78	inorder: regr-update: reduce dynamic mem. use to speedup sims ... previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)	2011-02-18 14:31:37 -05:00
Gabe Black	5ec5794456	X86: Update stats for the improved branch detection/prediction.	2011-02-13 17:46:04 -08:00
Gabe Black	44306e8114	X86: Update stats now that the dest reg isn't read unnecessarily to set flags.	2011-02-13 17:45:30 -08:00
Gabe Black	b046f3feb6	X86: Update stats for the reduced register reads.	2011-02-13 17:44:32 -08:00
Korey Sewell	2971b8401a	inorder:regress: host-inst-rate improved ~58% ... there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext) the latest changes to how instruction scheduling (how instructions figure out what they want to do on each pipeline stage in the inorder model) were able to improve performance by a nice amount... The latest results for the inorder model process about 100k insts/second (note: 58% is over the last time run on 64-bit pool machines at UM)	2011-02-12 10:14:52 -05:00
Ali Saidi	2055df8322	Stats: Update the statistics for vnc patch.	2011-02-11 18:29:36 -06:00
Brad Beckmann	4eab18fd06	regess: protocol regression tester updates	2011-02-08 18:07:54 -08:00
Brad Beckmann	ea9d4c3a97	memtest: due to contention increase, increased deadlock threshold	2011-02-08 15:53:33 -08:00
Gabe Black	0851580aad	Stats: Re update stats.	2011-02-07 19:23:13 -08:00
Gabe Black	1b64bfa933	Stats: Back out broken update.	2011-02-07 19:23:11 -08:00
Gabe Black	2107258d24	X86: Add stats for the new x86 fs regressions.	2011-02-07 01:23:16 -08:00
Gabe Black	dd53743797	X86: Add scripts to support X86 FS configurations in the regressions.	2011-02-07 01:23:02 -08:00
Brad Beckmann	45f881919f	regress: Regression Tester output updates	2011-02-06 22:14:23 -08:00
Gabe Black	55df9e348c	X86: Add o3 regressions in SE mode. ... Exclude bzip2 for now. It works, it just takes too long to run.	2011-02-05 00:16:09 -08:00
Gabe Black	0aafbe4098	X86: Update ruby stats for stupd change.	2011-02-04 03:47:23 -08:00
Korey Sewell	a48fe2729a	imported patch regression_updates	2011-02-04 00:09:22 -05:00
Gabe Black	00f24ae92c	Config: Keep track of uncached and cached ports separately. ... This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.	2011-02-03 20:23:00 -08:00
Gabe Black	54f88d84c2	Stats: Update the x86 stats to reflect changing stupd to a store and update.	2011-02-02 19:56:49 -08:00
Ali Saidi	f7885b8f26	ARM/O3: Add regressions for ARM w/ O3 CPU.	2011-01-18 16:30:06 -06:00
Ali Saidi	9b67f3723e	Stats: Update stats for previous set of patches.	2011-01-18 16:30:06 -06:00
Gabe Black	6fb521faba	SPARC: Update stats for the call r15 as source change.	2011-01-15 15:30:34 -08:00
Nilay Vaish	bec0103bb4	Regression Tests: Update the output for MESI_CMP_directory ... This patch updates the output for regression tests that are carried out on MESI_CMP_directory protocol. The changes made to the protocol in order to remove the bugs present result in regression failure for the 60.rubytest. Since the earlier protocol was incorrect, so we certainly cannot relay on the earlier reference output. Hence, the update.	2011-01-13 22:48:03 -06:00
Ali Saidi	1cfe2c8820	Stats: Fix stats for cumulative flags change.	2010-12-07 16:19:57 -08:00
Gabe Black	0e41d4e5ea	Stats: Update the O3 fetch stats for SPARC.	2010-11-15 19:37:15 -08:00
Ali Saidi	371110fb0a	Regressions: Update regressions for SIMD opclass changes	2010-11-15 14:04:05 -06:00
Ali Saidi	c370866331	ARM: Update regressions for CLCD and KMI additions	2010-11-15 14:04:03 -06:00
Ali Saidi	0b7967d606	Update EIO regressions for last set of patches	2010-11-10 00:48:03 -06:00
Ali Saidi	06c5283930	ARM: Update SE stats for TLB stats additions	2010-11-08 13:59:35 -06:00
Ali Saidi	fe300c6de2	ARM: Add full-system regressions	2010-11-08 13:58:25 -06:00
Ali Saidi	b4b6a2338a	ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.	2010-11-08 13:58:24 -06:00
Gabe Black	b53231e7fe	Ref output: Update refs for PCState change.	2010-10-31 00:07:48 -07:00
Steve Reinhardt	13a15c55a4	stats: update stats for previous cset ... Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.	2010-09-21 23:07:35 -07:00
Steve Reinhardt	0bd9cea340	diff-out: clean up options ... Make diff-out sort stats changes by percentage by default, with '-a' to use current alpha sort (instead of requiring '-p' to sort by percentage). Other minor options cleanup too.	2010-09-21 23:07:34 -07:00
Steve Reinhardt	db2f226834	tests: print if output files match ... Add '-s' flag to diff command generating outdiff file so we have positive confirmation when outputs match.	2010-09-21 23:07:34 -07:00