Commit graph

5449 commits

Author SHA1 Message Date
Andreas Hansson
72538294fb gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
2012-03-19 06:36:09 -04:00
Andreas Hansson
adb8621031 clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
2012-03-19 06:35:04 -04:00
Andreas Hansson
a444a6f8d6 scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those
cases when the port is not connected.
2012-03-19 06:34:02 -04:00
Brian Grayson
98185658c5 O3: Add fatal when fetchWidth > Impl::MaxWidth. 2012-03-11 10:20:54 -04:00
Brian Grayson
9a9a4a0780 ARM: Fix branch prediction issue with CB(N)Z instruction 2012-03-09 15:32:41 -05:00
Geoffrey Blake
69d229ce28 O3/Ozone: Eliminate dead code counting software prefetch insts
Eliminates dead code in the O3 and Ozone CPU models that counted
software prefetch instructions separately for the ALPHA ISA only.
2012-03-09 09:59:28 -05:00
Geoffrey Blake
98cf57fb89 CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.
2012-03-09 09:59:28 -05:00
Geoffrey Blake
043709fdfa CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.
2012-03-09 09:59:27 -05:00
Ali Saidi
df05ffab12 ARM: Don't reset CPUs that are going to be switched in. 2012-03-09 09:59:26 -05:00
Ali Saidi
3ce2d0fad0 System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
2012-03-09 09:59:26 -05:00
Ali Saidi
ec1ef24895 ARM: Fix valgrind reported error on O3 that was causing minor stats changes. 2012-03-09 09:59:26 -05:00
Ali Saidi
eaa994e7f6 cache: Allow main memory to be at disjoint address ranges. 2012-03-09 09:59:25 -05:00
Marc Orr
eb43883bef build scripts: Made minor modifications to reduce build overhead time.
1. --implicit-cache behavior is default.
2. makeEnv in src/SConscript is conditionally called.
3. decider set to MD5-timestamp
4. NO_HTML build option changed to SLICC_HTML (defaults to False)
2012-03-06 19:07:41 -08:00
Steve Reinhardt
fd2d5ae2af DynInst: get rid of dead MyHash code.
Not sure what this was ever used for, but it
doesn't seem used anymore.
2012-03-02 09:17:42 -08:00
Andreas Hansson
32eae8094d CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.

The patch also adds the "createInterruptController" call to a number
of the regression scripts.
2012-03-02 09:21:48 -05:00
Andreas Hansson
adc419a13a Ruby: Rename RubyPort::sendTiming to avoid overriding base class
This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.

In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.
2012-03-02 09:16:50 -05:00
Ali Saidi
b129d7ce00 ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
2012-03-02 08:18:19 -06:00
Ali Saidi
96e37eb17c ARM: FIx missing cf controller connection. 2012-03-01 22:43:23 -06:00
Chander Sudanthi
357fb0a185 VNC: spacing
Fixed some spacing in a switch statement
2012-03-01 17:26:36 -06:00
Ali Saidi
91b737ed48 ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
2012-03-01 17:26:31 -06:00
Ali Saidi
3876105bdb ARM: Add RTC device for ARM platforms.
This change implements a PL031 real time clock.

--HG--
rename : src/dev/arm/timer_sp804.cc => src/dev/arm/rtc_pl031.cc
rename : src/dev/arm/timer_sp804.hh => src/dev/arm/rtc_pl031.hh
2012-03-01 17:26:31 -06:00
Matt Horsnell
08187e3916 ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
2012-03-01 17:26:31 -06:00
Ali Saidi
d907d0ec72 Cache: Fix an issue with LRU when bonus block is used to complete transaction.
The block is never inserted because it's the one extra block in the cache, but
it can be invalidated twice in a row. In that case the block doesn't have a
new master id (beacuse it was never inserted), however it is valid and
the accounting goes wrong at that point.
2012-03-01 17:26:31 -06:00
Dam Sunwoo
86d1042d9f ARM: move kernel func event to correct location.
With the recent series of patches, the symbol table loading moved from
"construct" time to "init" time, but the kernel function event
callback registration was left behind. This patch moves it to the
proper location.
2012-03-01 17:26:31 -06:00
Giacomo Gabrielli
d51478db4e ARM: fix bits-to-fp conversion function declarations.
Add extra declarations to allow the compiler to pick up the right function.
Please note that these declarations have been added as part of the
clang-related changes.
2012-03-01 17:26:30 -06:00
Nilay Vaish
4b32c9fb4d x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
2012-03-01 11:37:03 -06:00
Nilay Vaish
c80af04d7d x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
2012-03-01 11:37:02 -06:00
Andreas Hansson
e5ac647fc9 MEM: Make all the port proxy members const
This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
2012-02-29 04:47:51 -05:00
Andreas Hansson
88abdc0fad SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
This patch fixes a compilation error that occurs with gcc >= 4.6.1,
caused by swig not including cstddef and not using the std:: namespace
prefix for ptrdiff_t. There is an old patch,
http://reviews.m5sim.org/r/913/ that no longer applies cleanly and
this might be re-iterating the same issue.

We work around the problem by always enforcing the inclusion of
cstddef in all swig interface declarations, and also by explicitly
using std::ptrdiff_t.
2012-02-29 04:26:58 -05:00
Gabe Black
559b43a372 X86: Use the M5PanicFault fault in execute methods instead of calling panic.
If an instruction is executed speculatively and hits a situation where it
wants to panic, it should return a fault instead. If the instruction was
misspeculated, the fault can be thrown away. If the instruction wasn't
misspeculated, the fault will be invoked and the panic will still happen.
2012-02-26 15:32:53 -08:00
Andreas Hansson
0cd0a8fdd3 MEM: Simplify cache ports preparing for master/slave split
This patch splits the two cache ports into a master (memory-side) and
slave (cpu-side) subclass of port with slightly different
functionality. For example, it is only the CPU-side port that blocks
incoming requests, and only the memory-side port that schedules send
events outside of what the transmit list dictates.

This patch simplifies the two classes by relying further on
SimpleTimingPort and also generalises the latter to better accommodate
the changes (introducing trySendTiming and scheduleSend). The
memory-side cache port overrides sendDeferredPacket to be able to not
only send responses from the transmit list, but also send requests
based on the MSHRs.

A follow on patch further simplifies the SimpleTimingPort and the
cache ports.
2012-02-24 11:52:49 -05:00
Andreas Hansson
77878d0a87 MEM: Prepare mport for master/slave split
This patch simplifies the mport in preparation for a split into a
master and slave role for the message ports. In particular,
sendMessageAtomic was only used in a single location and similarly so
sendMessageTiming. The affected interrupt device is updated
accordingly.
2012-02-24 11:50:15 -05:00
Andreas Hansson
86c2aad482 Ruby: Simplify tester ports by not using SimpleTimingPort
This patch simplfies the master ports used by RubyDirectedTester and
RubyTester by avoiding the use of SimpleTimingPort. Neither tester
made any use of the functionality offered by SimpleTimingPort besides
a trivial implementation of recvFunctional (only snoops) and
recvRangeChange (not relevant since there is only one master).

The patch does not change or add any functionality, it merely makes
the introduction of a master/slave port easier (in a future patch).
2012-02-24 11:48:48 -05:00
Andreas Hansson
485d103255 MEM: Move all read/write blob functions from Port to PortProxy
This patch moves the readBlob/writeBlob/memsetBlob from the Port class
to the PortProxy class, thus making a clear separation of the basic
port functionality (recv/send functional/atomic/timing), and the
higher-level functional accessors available on the port proxies.

There are only a few places in the code base where the blob functions
were used on ports, and they are all for peeking into the memory
system without making a normal memory access (in the memtest, and the
malta and tsunami pchip). The memtest also exemplifies how easy it is
to create a non-translating proxy if desired. The malta and tsunami
pchip used a slave port to perform a functional read, and this is now
changed to rely on the physProxy of the system (to which they already
have a pointer).
2012-02-24 11:46:39 -05:00
Andreas Hansson
9e3c8de30b MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would
not be complete without a port proxy by making the proxies members
rathen than dynamically allocated. In essence, if NULL would not be a
valid value for the proxy, then we avoid using a pointer to make this
clear.

The same approach is used for the methods using these proxies, such as
loadSections, that now use references rather than pointers to better
reflect the fact that NULL would not be an acceptable value (in fact
the code would break and that is how this patch started out).

Overall the concept of "using a reference to express unconditional
composition where a NULL pointer is never valid" could be done on a
much broader scale throughout the code base, but for now it is only
done in the locations affected by the proxies.
2012-02-24 11:45:30 -05:00
Andreas Hansson
1031b824b9 MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.

This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
2012-02-24 11:43:53 -05:00
Andreas Hansson
9f07d2ce7e CPU: Round-two unifying instr/data CPU ports across models
This patch continues the unification of how the different CPU models
create and share their instruction and data ports. Most importantly,
it forces every CPU to have an instruction and a data port, and gives
these ports explicit getters in the BaseCPU (getDataPort and
getInstPort). The patch helps in simplifying the code, make
assumptions more explicit, andfurther ease future patches related to
the CPU ports.

The biggest changes are in the in-order model (that was not modified
in the previous unification patch), which now moves the ports from the
CacheUnit to the CPU. It also distinguishes the instruction fetch and
load-store unit from the rest of the resources, and avoids the use of
indices and casting in favour of keeping track of these two units
explicitly (since they are always there anyways). The atomic, timing
and O3 model simply return references to their already existing ports.
2012-02-24 11:42:00 -05:00
Andreas Hansson
ef4af8cec8 MEM: Fatal when no port can be found for an address
This patch adds a check in the findPort method to ensure that an
invalid port id is never returned. Previously this could happen if no
default port was set, and no address matched the request, in which
case -1 was returned causing a SEGFAULT when using the id to index in
the port array. To clean things up further a symbolic name is added
for the invalid port id.
2012-02-24 11:40:29 -05:00
Steve Reinhardt
e121708e08 SimObject: make get_config_as_dict() tolerate undefined params
Without this patch, undefined params cause a cryptic KeyError
in multidict inside get_config_as_dict().  This patch lets
undefined params through get_config_as_dict() so they can
once again generate meaningful error messages later on in
the configuration process.
2012-02-20 08:11:14 -08:00
Andreas Hansson
6cf9f182f6 MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
2012-02-14 14:15:30 -05:00
Mrinmoy Ghosh
9b05e96b9e BPred: Fix RAS to handle predicated call/return instructions.
Change RAS to fix issues with predicated call/return instructions.
Handled all cases in the life of a predicated call and return instruction.
2012-02-13 12:26:25 -06:00
Mrinmoy Ghosh
fd90c3676d BP: Fix several Branch Predictor issues.
1. Updates the Branch Predictor correctly to the state
   just after a mispredicted branch, if a squash occurs.
2. If a BTB does not find an entry, the branch is predicted not taken.
   The global history is modified to correctly reflect this prediction.
3. Local history is now updated at the fetch stage instead of
   execute stage.
4. In the Update stage of the branch predictor the local predictors are
   now correctly updated according to the state of local history during
   fetch stage.

This patch also improves performance by as much as 17% on some benchmarks
2012-02-13 12:26:24 -06:00
Andreas Hansson
abc212461b MEM: Explicit ports and Python binding on CopyEngine
The copy-engine ports were previously created implicitly and bound
based on the dma port peer rather than relying on the normal Python
binding (connectPorts) being called explicitly. This patch makes the
copy engine port similar to all other ports in that they are visibly
in the Python class and bound using the normal explicit calls through
Python.
2012-02-13 06:46:43 -05:00
Andreas Hansson
63777fb23f MEM: Pass the ports from Python to C++ using the Swig params
This patch adds basic information about the ports in the parameter
classes to be passed from the Python world to the corresponding C++
object. Currently, the only information passed is the number of
connected peers, which for a Port is either 0 or 1, and for a
VectorPort reflects the size of the VectorPort. The default port of
the bus had to be renamed to avoid using the name "default" as a field
in the parameter class. It is possible to extend the Swig'ed
information further and add e.g. a pair with a description and size.
2012-02-13 06:45:11 -05:00
Andreas Hansson
5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Gabe Black
eada4268ef X86: open flags: Another patch from Vince Weaver 2012-02-12 16:41:29 -08:00
Anthony Gutierrez
542d0ceebc cpu: add separate stats for insts/ops both globally and per cpu model 2012-02-12 16:07:39 -06:00
Dam Sunwoo
230540e655 mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.
2012-02-12 16:07:39 -06:00
Ali Saidi
8aaa39e93d mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
2012-02-12 16:07:38 -06:00
Mrinmoy Ghosh
7e104a1af2 prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00
Gabe Black
5b557a314f SPARC: Make PSTATE and HPSTATE a BitUnion.
This gets rid of cryptic bits of code with lots of bit manipulation, and makes
some comments redundant.
2012-02-11 14:16:38 -08:00
Nilay Vaish
aa513a4a99 Ruby: Remove isTagPresent() calls from Sequencer.cc
This patch removes the calls to isTagPresent() from Sequencer.cc. These
calls are made just for setting the cache block to have been most recently
used. The calls have been folded in to the function setMRU().
2012-02-10 11:29:02 -06:00
Nilay Vaish
69d8600bf8 MESI: Add queues for stalled requests
This patch adds support for stalling the requests queued up at different
controllers for the MESI CMP directory protocol. Earlier the controllers
would recycle the requests using some fixed latency. This results in
younger requests getting serviced first at times, and can result in
starvation. Instead all the requests that need a particular block to be
in a stable state are moved to a separate queue, where they wait till
that block returns to a stable state and then they are processed.
2012-02-10 11:05:24 -06:00
Nilay Vaish
72f3f526fc sim/system: initialize the pagePtr variable 2012-02-10 09:52:32 -06:00
Nilay Vaish
6a7a6263e1 O3 CPU: Improve handling of delayed commit flag
The delayed commit flag is used in conjunction with interrupt pending flag to
figure out whether or not fetch stage should get more instructions. This patch
clears this flag when instructions are squashed. Also, in case an interrupt is
pending, currently it is not possible to access the instruction cache. This
patch allows accessing the cache in case this flag is set.
2012-02-10 08:37:31 -06:00
Nilay Vaish
cd765c23a2 O3 CPU: Strengthen condition for handling interrupts
The condition for handling interrupts is to check whether or not the cpu's
instruction list is empty. As observed, this can lead to cases in which even
though the instruction list is empty, interrupts are handled when they should
not be. The condition is being strengthened so that interrupts get handled only
when the last committed microop did not had IsDelayedCommit set.
2012-02-10 08:37:30 -06:00
Nilay Vaish
8f7e03d4cf O3 CPU: Provide the squashing instruction
This patch adds a function to the ROB that will get the squashing instruction
from the ROB's list of instructions. This squashing instruction is used for
figuring out the macroop from which the fetch stage should fetch the microops.
Further, a check has been added that if the instructions are to be fetched
from the cache maintained by the fetch stage, then the data in the cache should
be valid and the PC of the thread being fetched from is same as the address of
the cache block.
2012-02-10 08:37:28 -06:00
Nilay Vaish
0e597e944a O3 Fetch: Check if PC is pointing to Microcode ROM 2012-02-10 08:37:26 -06:00
Gabe Black
e80ebc308f SE/FS: Record the system pointer all the time for the simple CPU.
This pointer was only being stored in code that came from SE mode. The system
pointer is always meaningful and available, so it should always be stored.
2012-02-10 02:05:31 -08:00
Andreas Hansson
cdb32860b4 MEM: Remove onRetryList from BusPort and rely on retryList
This patch removes the onRetryList field from the BusPort class and
entirely relies on the retryList which holds all ports that are
waiting to retry. The onRetryList field and the retryList were
previously used with overloaded functionalities and only one is really
needed (there were also checks to assert they held the same
information). After this patch the bus ports will be split into master
and slave ports and this simplifies that transition.
2012-02-09 13:06:27 -05:00
Gabe Black
a6246bb047 Checker: Access workload element 0 only if there is an element 0. 2012-02-07 04:44:01 -08:00
Gabe Black
f2b46fdb85 Faults: Turn off arch/faults.hh
Because there are no longer architecture independent but specialized functions
in arch/XXX/faults.hh, code that isn't using the faults from a particular ISA
no longer needs to be able to include them through the switching header file
arch/faults.hh. By removing that header file (arch/faults.hh), the potential
interface between ISA code and non ISA code is narrowed.
2012-02-07 04:43:21 -08:00
Gabe Black
cbcdcd53a7 System: Forgot to qrefresh with my last change. 2012-02-03 09:48:10 -08:00
Gabe Black
acebd9bf91 System: Fix the check which detects running out of physical memory.
The code that checks whether pages allocated by allocPhysPages only checks
that the first page fits into physical memory, not that all of them do. This
change makes the code check the last page which should work properly. This
function used to only allocate one page at a time, so the first page and last
page used to be the same thing.
2012-02-02 23:54:25 -08:00
Ali Saidi
0a26883296 configs: More fixes for the memory system updates 2012-02-01 09:48:28 -08:00
Gabe Black
ea8b347dc5 Merge with head, hopefully the last time for this batch. 2012-01-31 22:40:08 -08:00
Koan-Sin Tan
7d4f187700 clang: Enable compiling gem5 using clang 2.9 and 3.0
This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.
2012-01-31 12:05:52 -05:00
Andreas Hansson
4590b91fb8 MEM: Remove the otherPort from the cache ports
This patch is a very straight-forward simplification, removing the
unecessary otherPort pointer from the cache port. The pointer was only
used to forward range changes, and the address range is fixed for the
cache. Removing the pointer simplifies the transition to master/slave
ports.
2012-01-31 11:51:19 -05:00
Andreas Hansson
4fdecae443 Thread: Use inherited baseCpu rather than cpu in SimpleThread
This patch is a trivial simplification, removing the cpu pointer from
SimpleThread and relying on the baseCpu pointer in ThreadState. The
patch does not add or change any functionality, it merely cleans up
the code.
2012-01-31 11:50:07 -05:00
Dam Sunwoo
0ed3c84c7b util: implements "writefile" gem5 op to export file from guest to host filesystem
Usage: m5 writefile <filename>

File will be created in the gem5 output folder with the identical filename.
Implementation is largely based on the existing "readfile" functionality.
Currently does not support exporting of folders.
2012-01-31 07:46:04 -08:00
Geoffrey Blake
af6aaf2581 CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU.  These changes have only been tested with the ARM ISA.  Other
ISAs potentially require modification.
2012-01-31 07:46:03 -08:00
Gabe Black
e88165a431 Merge with main repository. 2012-01-30 21:07:57 -08:00
Andreas Hansson
cfc268ad9e MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
This patch makes the physMemPort of the RubyPort a PioPort rather than
an M5Port. This reflects the fact that the M5Port and PioPort have
different roles. The M5Port is really a coherent slave that is
connected to the CPUs and other coherent masters of the system,
e.g. DMA ports. The PioPort, on the other hand, is a master port that
is connected to the memory and other slaves, for example the pio
devices.

This simplifies future changes into master/slave ports and is
consistent with the port roles throughout the system.
2012-01-30 05:38:24 -05:00
Andreas Hansson
ef9fc01073 MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
This patch cleans up forward declarations and a member-function
prototype that still referred to the old FunctionalPort, VirtualPort
and TranslatingPort. There is no change in functionality.
2012-01-30 03:44:25 -05:00
Gabe Black
39f314cc15 Yet another merge with the main repository.
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
2012-01-29 03:27:15 -08:00
Gabe Black
dc0e629ea1 Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
2012-01-29 02:04:34 -08:00
Nilay Vaish
5c2fc35e02 O3 CPU LSQ: Implement TSO
This patch makes O3's LSQ maintain total order between stores. Essentially
only the store at the head of the store buffer is allowed to be in flight.
Only after that store completes, the next store is issued to the memory
system. By default, the x86 architecture will have TSO.
2012-01-28 19:09:04 -06:00
Gabe Black
ec20ee2f7c SE/FS: Make SE vs. FS mode a runtime parameter. 2012-01-28 07:24:34 -08:00
Gabe Black
eab5c60286 MIPS: Fix a compiler warning from the eret instruction. 2012-01-28 07:24:23 -08:00
Gabe Black
c3d41a2def Merge with the main repo.
--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-28 07:24:01 -08:00
Andreas Hansson
4acca8a053 ns_gige: Fix a missing curly brace in if-statement
This patch adds a missing curly brace when clearing and setting the
appropriate bits in the ns_gige.cc code.

This commit is not based on any runtime bug experienced, but rather
inspection of the code.
2012-01-27 12:54:11 -05:00
Gabe Black
da2a4acc26 Merge yet again with the main repository. 2012-01-16 04:27:10 -08:00
Mitchell Hayenga
698408bce2 Fix memory corruption issue with CopyStringOut()
CopyStringOut() improperly indexed setting the null
character, would result in zeroing a random byte
of memory after(out of bounds) the character array.
2012-01-12 15:27:20 -06:00
Ali Saidi
bd55c9e2af sim: display final value of curTick in stats
Different from sim_ticks in that this value is restored from checkpoints and is never reset.
Useful for aligning with framebuffer output ticks
2012-01-25 17:18:25 +00:00
Ali Saidi
e1c48dfce5 Mem: Add simple bandwidth stats to PhysicalMemory 2012-01-25 17:18:25 +00:00
Nilay Vaish
63563c9df2 O3, Ruby: Forward invalidations from Ruby to O3 CPU
This patch implements the functionality for forwarding invalidations and
replacements from the L1 cache of the Ruby memory system to the O3 CPU. The
implementation adds a list of ports to RubyPort. Whenever a replacement or an
invalidation is performed, the L1 cache forwards this to all the ports, which
is the LSQ in case of the O3 CPU.
2012-01-23 11:07:14 -06:00
Nilay Vaish
9481d05b8a MemCmd: Add a command for invalidation requests to LSQ
This command will be sent from the memory system (Ruby) to the LSQ of
an O3 CPU so that the LSQ, if it needs to, invalidates the address in
the request packet.
2012-01-23 11:07:11 -06:00
Andreas Hansson
acd289b7ef MEM: Make the bus default port yet another port
This patch removes the idiosyncratic nature of the default bus port
and makes it yet another port in the list of interfaces. Rather than
having a specific pointer to the default port we merely track the
identifier of this port. This change makes future port diversification
easier and overall cleans up the bus code.
2012-01-17 12:55:09 -06:00
Andreas Hansson
55cf3f4ac1 MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.
2012-01-17 12:55:09 -06:00
Andreas Hansson
2208ea049f MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.

In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.
2012-01-17 12:55:09 -06:00
William Wang
e731cf4c1d MEM: Remove the functional ports from the memory system
The functional ports are no longer used and this patch cleans up the
legacy that is still present in buses, memories, CPUs etc. Note that
this does not refer to the class FunctionalPort (already removed), but
rather ports with the name (and use) functional.
2012-01-17 12:55:09 -06:00
Andreas Hansson
07cf9d914b MEM: Separate queries for snooping and address ranges
This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.
2012-01-17 12:55:09 -06:00
Andreas Hansson
142380a373 MEM: Remove Port removeConn and MemObject deletePortRefs
Cleaning up and simplifying the ports and going towards a more strict
elaboration-time creation and binding of the ports.
2012-01-17 12:55:09 -06:00
Andreas Hansson
6315e5bbb5 MEM: Remove the notion of the default port
This patch removes the default port and instead relies on the peer
being set to NULL initially. The binding check (i.e. is a port
connected or not) will eventually be moved to the init function of the
modules.
2012-01-17 12:55:09 -06:00
Andreas Hansson
de34e49d15 MEM: Simplify ports by removing EventManager
This patch removes the inheritance of EventManager from the ports and
moves all responsibility for event queues to the owner. Eventually the
event manager should be the interface block, which could either be the
structural owner or a subblock like a LSQ in the O3 CPU for example.
2012-01-17 12:55:09 -06:00
Andreas Hansson
b3f930c884 CPU: Moving towards a more general port across CPU models
This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
2012-01-17 12:55:08 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Andreas Hansson
43a45edcf0 Ruby: Change the access permissions for MOESI hammer
This patch changes the access permission for the WB_E_W state from
Busy to Read_Write to avoid having issues in follow-on patches with
functional accesses going through Ruby. This change was made after
consultation with all involved parties and is more of a work-around
than a fix.
2012-01-17 12:55:07 -06:00
Andreas Hansson
41af57f9fb MEM: Add the system port as a central access point
The system port is used as a globally reachable access point to the
memory subsystem. The benefit of using an actual port is that the
usual infrastructure is used to resolve any access and thus makes the
overall system able to handle distributed memories in any
configuration, and also makes the accesses agnostic to the address
map. This patch only introduces the port and does not actually use it
for anything.
2012-01-17 12:55:07 -06:00
Andreas Hansson
13ef7a5647 MEM: Differentiate functional cache accesses from CPU and memory
This patch changes the functionalAccess member function in the cache
model such that it is aware of what port the access came from, i.e. if
it came from the CPU side or from the memory side. By adding this
information, it is possible to respect the 'forwardSnoops' flag for
snooping requests coming from the memory side and not forward
them. This fixes an outstanding issue with the IO bus getting accesses
that have no valid destination port and also cleans up future changes
to the bus model.
2012-01-17 12:55:07 -06:00
Steve Reinhardt
7a3a37307a Alpha: warn_once about broken PAL breakpoints.
A recent changeset (aae12ce9f34c) removed support for
PAL-mode breakpoints in Alpha, since it was awkward
and likely unused.  This patch lets a user know if they
potentially run into this limitation.
2012-01-16 19:01:27 -08:00
Steve Reinhardt
1585cfb5b5 debug: fix AllFlags::disable()
Looks like copy-and-paste bug, apparently I'm the first
person to ever use this since it's plainly broken.
2012-01-16 19:00:59 -08:00
Maximilien Breughe
a7394ad680 inorder: MDU deadlock fix 2012-01-12 10:15:00 -05:00
Deyuan Guo
4a59cf00b4 mips: compatibility between MIPS_SE and cross compiler from CodeSorcery 2012-01-12 09:59:01 -05:00
Deyuan Guo
31b6941a52 mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FS 2012-01-12 09:59:00 -05:00
Deyuan Guo
a40ec5671f mips: Fix decoder of two float-convert instructions 2012-01-12 09:58:59 -05:00
Deyuan Guo
7f782a6c79 mips: definition of MIPS64_QNAN in registers.hh 2012-01-12 09:58:58 -05:00
Nilay Vaish
0e6d6a5e25 PerfectCacheMemory: Remove references to CacheMsg
The definition for the class CacheMsg was removed long back. Some declaration
had still survived, which was recently removed. Since the PerfectCacheMemory
class relied on this particular declaration, its absence let to compilation
breaking down. Hence this patch.
2012-01-12 00:35:57 -06:00
Ali Saidi
c40ae2c3fb Packet: Put back part of the assert 2012-01-11 19:27:11 -05:00
Ali Saidi
bc1c21274e Packet: Remove meaningless assert statement 2012-01-11 19:24:13 -05:00
Nilay Vaish
bf59a9298f Ruby: Resurrect Cache Warmup Capability
This patch resurrects ruby's cache warmup capability. It essentially
makes use of all the infrastructure that was added to the controllers,
memories and the cache recorder.
2012-01-11 13:48:48 -06:00
Nilay Vaish
3f8065290a Ruby Debug Flags: Remove one, add another
The flag RubyStoreBuffer is being removed, instead RubySystem is being added
2012-01-11 13:42:00 -06:00
Nilay Vaish
2d3cae02f5 Ruby Port: Add a list of cpu ports attached to this port 2012-01-11 13:39:58 -06:00
Nilay Vaish
17fc60ee88 Ruby EventQueue: Remove unused functions 2012-01-11 13:31:04 -06:00
Nilay Vaish
8b3ad17cc3 Ruby Sparse Memory: Add function for collating blocks
This patch adds function to the Sparse Memory so that the blocks can be
recorded in a cache trace. The blocks are added to the cache recorder
which can later write them into a file.
2012-01-11 13:29:54 -06:00
Nilay Vaish
c3109f7775 Ruby: Add infrastructure for recording cache contents
This patch changes CacheRecorder, CacheMemory, CacheControllers
so that the contents of a cache can be recorded for checkpointing
purposes.
2012-01-11 13:29:15 -06:00
Nilay Vaish
ab0347a1c6 Ruby Memory Vector: Functions for collating and populating pages
This patch adds functions to the memory vector class that can be used for
collating memory pages to raw trace and for populating pages from a raw
trace.
2012-01-11 11:46:23 -06:00
Nilay Vaish
bd739a75b9 Ruby: remove the files related to the tracer
The Ruby Tracer is out of date with the changes that are being carried
out to support checkpointing. Hence, it needs to be removed.
2012-01-10 18:35:45 -06:00
Nilay Vaish
70cb16ba14 MOESI Hammer: Remove a couple of bugs
A couple of bugs were observed while building checkpointing support in Ruby.
This patch changes transitions to remove those errors.
2012-01-10 17:28:44 -06:00
Nilay Vaish
adff204c97 Sparse Memory: Simplify the structure for an entry
The SparseMemEntry structure includes just one void* pointer. It seems
unnecessary that we have a structure for this. The patch removes the
structure and makes use of a typedef on void* instead.
2012-01-10 10:20:32 -06:00
Ali Saidi
cfa1d26b43 Automated merge with ssh://repo.gem5.org/gem5 2012-01-10 10:18:08 -06:00
Ali Saidi
8f18898e85 config: Fix json output for Python lt 2.6. 2012-01-10 10:17:33 -06:00
Nilay Vaish
9957035a42 DPRINTF: Improve some dprintf messages. 2012-01-10 10:15:02 -06:00
Nilay Vaish
acbc03ae46 X86: Add memory fence to I/O instructions 2012-01-09 20:13:31 -06:00
Anders Handler
b587d511c3 CPU: Remove Alpha-specific PC alignment check. 2012-01-09 20:05:07 -05:00
Ali Saidi
e308208f30 Config: Fix issue with JSON output 2012-01-09 20:04:28 -05:00
Geoffrey Blake
e826d23a2e Packet: Add derived class FunctionalPacket to enable partial functional reads
This adds the derived class FunctionalPacket to fix a long standing
deficiency in the Packet class where it was unable to handle finding data to
partially satisfy a functional access.  Made this a derived class as
functional accesses are used only in certain contexts and to not add any
additional overhead to the existing Packet class.
2012-01-09 18:10:05 -06:00
Dam Sunwoo
bda1125e88 stats: fix Vector2d to display stats correctly when y_subname is not specified.
Vector2d stats with no y_subname were not displayed as the VectorPrint subname was not initialized correctly to reflect the empty field.
2012-01-09 18:08:20 -06:00
Prakash Ramrakhyani
51aa7e4a03 sim: Enable sampling of run-time for code-sections marked using pseudo insts.
This patch adds a mechanism to collect run time samples for specific portions
of a benchmark, using work_begin and work_end pseudo instructions.It also enhances
the histogram stat to report geometric mean.
2012-01-09 18:08:20 -06:00
Ali Saidi
525d1e46dc O3: Remove some asserts that no longer seem to be valid. 2012-01-09 18:08:20 -06:00
Ali Saidi
68d387ec80 config: support outputing a pickle of the configuration tree 2012-01-09 18:08:20 -06:00
Min Kyu Jeong
c94e5256d9 mem: Change DPRINTF prints more useful destination port number.
Old code prints 0 for destination since pkt->getDest() returns 0 for
pkt->getDest() == Packet::Broadcast, which is always true.
2012-01-09 18:08:20 -06:00
Ali Saidi
d2c26f402c O3: Add support of function tracing with O3 CPU. 2012-01-09 18:08:20 -06:00
Ali Saidi
bcb71963eb ARM: Add support for running multiple systems 2012-01-09 18:08:20 -06:00
Ali Saidi
80a6907927 ARM: Add support for initparam m5 op 2012-01-09 18:08:20 -06:00
Dam Sunwoo
3f9e352de4 Base: Fixed shift amount in genrand() to work with large numbers
The previous version didn't work correctly with max integer values (2^31-1 for
32-bit, 2^63-1 for 64bit version), causing "shift" to become -1.  For smaller
numbers, it wouldn't have caused functional errors, but would have resulted in
more than necessary loops in the while loop.  Special-cased cases when (max + 1
== 0) to prevent the ceilLog2 functions from failing.
2012-01-09 18:08:20 -06:00
Andreas Hansson
59b7cad3ec SWIG: Make gem5 compile and link with swig 2.0.4
To make gem5 compile and run with swig 2.0.4 a few minor fixes are
necessary, the fail label issues by swig must not be treated as an
error by gcc (tested with gcc 4.2.1), and the vector wrappers must
have SWIGPY_SLICE_ARG defined which happens in pycontainer.swg,
included through std_container.i. By adding the aforementioned include
to the vector wrappers everything seems to work.
2012-01-09 18:08:20 -06:00
Andreas Hansson
c2dbfc1d6c MAC: Make gem5 compile and run on MacOSX 10.7.2
Adaptations to make gem5 compile and run on OSX 10.7.2, with a stock
gcc 4.2.1 and the remaining dependencies from macports, i.e. python
2.7,.2 swig 2.0.4, mercurial 2.0. The changes include an adaptation of
the SConstruct to handle non-library linker flags, and Darwin-specific
code to find the memory usage of gem5. A number of Ruby files relied
on ambigious uint (without the 32 suffix) which caused compilation
errors.
2012-01-09 18:08:20 -06:00
Nilay Vaish
10c2e8ae9a Ruby Cache: Add param for marking caches as instruction only 2012-01-07 07:38:53 -06:00
Gabe Black
241cc0c840 Another merge with the main repository. 2012-01-07 02:16:37 -08:00
Gabe Black
ec936364b7 Merge with the main repository again. 2012-01-07 02:15:35 -08:00
Gabe Black
36a822f08e Merge with main repository. 2012-01-07 02:10:34 -08:00
Nilay Vaish
ce941fd2ae AbstractController: Remove some of the unused functions
--HG--
extra : rebase_source : 78df7398a609f1db8a2592cd2d1bdc9156d1b8c3
2012-01-06 05:11:07 -06:00
Nilay Vaish
6da125cc3c Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hh
This constant is currently in System.hh, but is only used in Set.hh. It
is being moved to Set.hh to remove this artificial dependence of Set.hh
on System.hh.

--HG--
extra : rebase_source : 683c43a5eeaec4f5f523b3ea32953a07f65cfee7
2012-01-06 05:11:07 -06:00
Nilay Vaish
daa4c7526a eventq: add a function for replacing head of the queue
This patch adds a function for replacing the event at the head of the queue
with another event. This helps in running a different set of events. Events
already scheduled can processed by replacing the original head event back.
This function has been specifically added to support cache warmup and
cooldown required for creating and restoring checkpoints.

--HG--
extra : rebase_source : ed6e2905720b6bfdefd020fab76235ccf33d28d1
2012-01-05 11:02:56 -06:00
Nilay Vaish
d3aa01eed9 MESI Coherence Protocol: Fix L2 miss statistics
This patch removes calls to uu_ProfileMiss from transitions where the request
is satisfied by the L2 cache controller.

--HG--
extra : rebase_source : e59fe7c6cd5795c0019cf178dd3b062d73cc2ff5
2012-01-05 11:00:45 -06:00
Nilay Vaish
bd23a37198 X86 TLB: Move a DPRINTF to its correct place
The DPRINTF for doing protection checks appears after the checks have been
carried out. It is possible that the function returns while the checks are
being carried, in which case the printf is missed out. This patch moves the
DPRINTF before the checks.

--HG--
extra : rebase_source : 172896057e593022444d882ea93323a5d9f77a89
2012-01-05 11:00:32 -06:00
Nilay Vaish
ea94029ea5 Ruby: Shuffle some of the included files
This patch adds and removes included files from some of the files so as to
organize remove some false dependencies and include some files directly
instead of transitively.

--HG--
extra : rebase_source : 09b482ee9ae00b3a204ace0c63550bc3ca220134
2011-12-31 18:44:51 -06:00
Nilay Vaish
734ef9a209 SLICC: Use pointers for directory entries
SLICC uses pointers for cache and TBE entries but not for directory entries.
This patch changes the protocols, SLICC and Ruby memory system so that even
directory entries are referenced using pointers.

--HG--
extra : rebase_source : abeb4ac78033d003153751f216fd1948251fcfad
2011-12-31 16:38:30 -06:00
Ali Saidi
94ce971278 IO: Fix bug in DMA Device where receiving a snoop on DMA port would cause a panic.
--HG--
extra : rebase_source : 8152d4fa7d7354c9f150a450ae0710e95141ba4b
2011-12-15 00:09:46 -05:00
Nathan Binkert
6ef9691035 gcc: fix unused variable warnings from GCC 4.6.1
--HG--
extra : rebase_source : f9e22de341493a25ac6106c16ac35c61c128a080
2011-12-13 11:49:27 -08:00
Ali Saidi
9b52717a92 Trace: FIx issue with creation of trace file with output dir overhaul.
--HG--
extra : rebase_source : c1ab57ea8805703d97cdee4f32410821a2d2a9db
2011-12-01 17:36:22 -08:00
Brad Beckmann
8daad28a90 MOESI_hammer: fixed L2 to L1 infinite stalls and deadlock
--HG--
extra : rebase_source : 90f217f28e195a8cee5d64b25c913b452d818676
2011-12-01 10:08:52 -08:00
Brad Beckmann
cecbdb6d79 physmem: Improved fatal message for size mismatch
--HG--
extra : rebase_source : 16da1c63263f8fd6fef9a842c577343cd6246a35
2011-12-01 10:08:52 -08:00
Chris Emmons
9aea847f58 VNC: Add support for capturing frame buffer to file each time it is changed.
When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory.  Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

--HG--
extra : rebase_source : d4e08e83f4fa6ff79f3dc9c433fc1f0487e057fc
2011-12-01 00:15:26 -08:00
Chris Emmons
5bde1d359f Output: Add hierarchical output support and cleanup existing codebase.
--HG--
extra : rebase_source : 3301137733cdf5fdb471d56ef7990e7a3a865442
2011-12-01 00:15:25 -08:00
Ali Saidi
5d50ee420d SE: Don't warn when not extending stack as it's too noisy with O3.
--HG--
extra : rebase_source : e56d1551d42d46b5f357cd63f9891715b664f6fc
2011-12-01 00:15:25 -08:00
Chander Sudanthi
61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-12-01 00:15:22 -08:00
Mitchell Hayenga
fa753c1454 Device: Make changes necessary to support a coherent page walker cache.
Adds the flag 'recvSnoops' which enables pagewalkers using DmaPorts,
to properly configure snoops.

--HG--
extra : rebase_source : 64207bef62c3268ddff2236ee4adae873812325f
2011-12-01 00:15:22 -08:00
Ali Saidi
946f7f0f55 ARM: Add support for having a TLB cache.
--HG--
extra : rebase_source : 7a5780ab74d7c294682738c7ccb3ce8d56c6fd63
2011-12-01 00:15:22 -08:00
Ali Saidi
5901c5223f ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .
Squashes the subsequent instructions in O3 pipe after the service call, so that
they see the effect of the system call when re-executed. This isn't really an issue
with FS mode, but can show up in SE mode.

--HG--
extra : rebase_source : 613a69fe1d9834261e25a8cd340aa6b47578e1fe
2011-12-01 00:15:22 -08:00
Ali Saidi
1444103998 O3: Add stat that counts how many cycles the O3 cpu was quiesced.
--HG--
extra : rebase_source : 043b9307eef3c5b87f8e6370765641e016ed1fa7
2011-12-01 00:15:22 -08:00
Gabe Black
93fb460fad X86: Fix a bad segmentation check for the stack segment.
--HG--
extra : rebase_source : 755f4f6eae52f88ed516a1f1ac9e2565725d89c1
2011-12-01 00:17:14 -05:00
Gabe Black
87b66c9ae3 SPARC: Minor style fix.
I forgot to fix this as well per Ali's feedback.

--HG--
extra : rebase_source : e70d031cb5f91e2212a1a73ea1769bf0549b826c
2011-11-28 04:35:55 -05:00
Andreas Hansson
64ccfecf95 SPARC: Fixing a minor copy-paste bug using the wrong variable
There was a bug in the mm_disk implementation where a copy paste error
resulted in the d32 variable not being initialised (as it incorrectly
was used instead of d16), and gcc 4.5 complaining.

--HG--
extra : rebase_source : 9515e87b188b9eac189da8034cb13c3bf7d9e20b
2011-11-28 04:34:18 -05:00
Gabe Black
e7d0c999a1 SPARC: Isolate FP operations enough to prevent code/rounding mode reordering.
--HG--
extra : rebase_source : ee79ab89c5a707c1294f38abb84c60f8ef64196c
2011-11-27 22:00:58 -05:00
Gabe Black
13552dc304 Compiler: Add an M5_NO_INLINE define.
--HG--
extra : rebase_source : 1f5e8b7bb6b0a8bb4f951b6d7189964d96ed5df1
2011-11-27 22:00:57 -05:00
Tushar Krishna
88e91cafc6 Topology: bug fix in external link initialization
--HG--
extra : rebase_source : c226cd1e5e5ed4d4c64fa9427de4905bd8335e34
2011-11-23 16:34:13 -05:00
Tushar Krishna
eff430a972 Remove standard_1level_CMP-protocol.sm include statement from Network
--HG--
extra : rebase_source : 51a2dd4bb643e3dc5b0218a6190cf5c1989f9691
2011-11-22 20:11:18 -05:00
Gabe Black
49a2d54e1a X86: Fix the constant detecting three byte opcodes in the predecoder.
--HG--
extra : rebase_source : b64c3d2348cb73177024695fb6e205d51bf1cda9
2011-11-20 05:10:05 -08:00
Gabe Black
85424bef19 SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
Gabe Black
de21bb93ea SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
Nilay Vaish
f3b4d10a05 Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.
2011-11-14 17:44:35 -06:00
Gabe Black
ec32d85f9d Power: Add a stubbed out stacktrace.cc 2011-11-13 12:40:15 -08:00
Gabe Black
ff4ba82610 POWER: Add a stub implementation of initCPU. 2011-11-13 12:40:15 -08:00
Gabe Black
1a8f1809fa Power: Add a stub kernel_stats.hh. 2011-11-13 12:40:15 -08:00
Gabe Black
5fcd11eaa5 SE/FS: Get rid of FULL_SYSTEM in dev. 2011-11-13 02:05:32 -08:00
Gabe Black
362a53e572 SE/FS: Get rid of FULL_SYSTEM in kern. 2011-11-13 02:05:32 -08:00
Gabe Black
6d68887c87 Power: Implement a stub for getArgument. 2011-11-13 02:05:27 -08:00
Gabe Black
2ee59cee1b GCC: Guard some gcc flags so they're used when available and needed. 2011-11-09 21:48:28 -08:00
Gabe Black
71c4534ce9 SE/FS: Get rid of FULL_SYSTEM in mem. 2011-11-07 01:13:43 -08:00
Gabe Black
812277ac6a SE/FS: Remove FULL_SYSTEM from swig. 2011-11-07 01:06:54 -08:00
Tushar Krishna
ac993964a9 GARNET: adding a fault model for resilient on-chip network research.
This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
2011-11-04 18:40:22 -04:00
Nilay Vaish
5ff6e05ffd MESI Protocol: Add functions for profiling misses 2011-11-04 11:26:12 -05:00
Nilay Vaish
582ea4d543 x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
2011-11-03 22:52:21 -05:00
Nilay Vaish
fb5c095cd5 Protocol: Remove standard one and two level files 2011-11-03 22:52:02 -05:00
Nilay Vaish
a547cf34b9 Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.
2011-11-03 22:46:45 -05:00
Gabe Black
8b4a3f4070 SE/FS: Get rid of FULL_SYSTEM in sim. 2011-11-02 02:11:14 -07:00
Gabe Black
fb15604f2c SE/FS: Get FULL_SYSTEM out of base/remote_gdb.cc. 2011-11-02 01:27:45 -07:00
Gabe Black
239b33e016 SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
Gabe Black
7b417d4188 SE/FS: Get rid of the last use of FULL_SYSTEM in x86. 2011-11-01 04:01:15 -07:00
Gabe Black
b6da5e2086 SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. 2011-11-01 04:01:14 -07:00
Gabe Black
1268e0df1f SE/FS: Expose the same methods on the CPUs in SE and FS modes. 2011-11-01 04:01:13 -07:00
Gabe Black
eeb85a8575 SE/FS: Remove the last uses of FULL_SYSTEM from SPARC. 2011-10-31 02:58:24 -07:00
Gabe Black
8ad2b8c559 SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
Gabe Black
d735abe5da GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
2011-10-31 01:09:44 -07:00
Gabe Black
ef097eb69c SE/FS: Build the solaris object in both SE and FS. 2011-10-30 18:52:30 -07:00
Gabe Black
248033f31e SE/FS: Get rid of FULL_SYSTEM in MIPS. 2011-10-30 18:39:38 -07:00
Gabe Black
8009b53c41 SE/FS: Compile in system events in SE mode. 2011-10-30 17:38:11 -07:00
Gabe Black
37a437893e System: Push boot_cpu_frequency down into the subclasses that actually use it.
This parameter depends on a number of coincidences to work properly. First,
there must be an array assigned to system called "cpu" even though there's no
parameter called that. Second, the items in the "cpu" array have to have a
"clock" parameter which has a "frequency" member. This is true of the normal
CPUs, but isn't true of the memory tester CPUs. This happened to work before
because the memory tester CPUs were only used in SE mode where this parameter
was being excluded. Since everything is being pulled into a common binary,
this won't work any more. Since the boot_cpu_frequency parameter is only used
by Alpha's Linux System object (and Mips's through copy and paste), the
definition of that parameter is moved down to those objects specifically.
2011-10-30 17:38:09 -07:00
Nilay Vaish
49c64731fa Python: Remove import for random 2011-10-30 15:55:32 -05:00
Gabe Black
b144f05b53 SE/FS: Remove the last references to FULL_SYSTEM from POWER. 2011-10-30 03:55:24 -07:00
Gabe Black
6dc3cedc4e X86: Build the same files in SE and FS. 2011-10-30 03:06:40 -07:00
Gabe Black
ca77249b0c SE/FS: Build syscall_emul.cc in FS mode. 2011-10-30 03:06:37 -07:00
Gabe Black
0c81db77f2 SE/FS: Make the system object more consistent between SE and FS. 2011-10-30 02:30:55 -07:00
Gabe Black
1d8822a364 X86: Get rid of more uses of FULL_SYSTEM. 2011-10-30 00:33:02 -07:00
Gabe Black
facb40f3ff SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. 2011-10-30 00:33:02 -07:00
Gabe Black
5b433568f0 SE/FS: Build the base process class in FS. 2011-10-30 00:32:54 -07:00
Nilay Vaish
706323fa21 Merged with recent changes. 2011-10-28 13:04:33 -05:00
Nilay Vaish
cbaebb3b5e Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.
2011-10-28 13:00:35 -05:00
Steve Reinhardt
6f9d294e86 SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back
through the Process to allocate memory, but did not have
a method to map addresses without allocating new pages.
It makes more sense for Process to do the allocation, so
this method was renamed allocateMem() and moved to Process,
and uses a new map() call on PageTable.

The remaining uses of the process pointer in PageTable
were only to get the name and the PID, so by passing these
in directly in the constructor, we can make PageTable
completely independent of Process.
2011-10-22 22:30:08 -07:00
Steve Reinhardt
4d5f2c28a8 syscall_emul: implement MAP_FIXED option to mmap() 2011-10-22 22:30:07 -07:00
Steve Reinhardt
38aef4c4c7 dev: clean up PioDevice and DmaDevive getPort() methods.
Make DmaDevice::getPort() call PioDevice::getPort() instead
of just copying and pasting the code.

Also move definitions from .hh to .cc file.
2011-10-20 13:11:56 -07:00
Steve Reinhardt
7b500f56ca SimObject: add export_method* hooks to export C++ methods to Python
Replace the (broken as of previous changeset) swig_objdecl() method
that allowed/forced you to substitute a whole new C++ struct
definition for SWIG to wrap with a set of export_method* hooks
that let you just declare a set of C++ methods (or other declarations)
that get inserted in the auto-generated struct.

Restore the System get/setMemoryMode methods, and use this mechanism
to specialize SimObject as well, eliminating teh need for sim_object.i.
Needed bits of sim_object.i are moved to the new pyobject.i.
Also sucked a little SimObject specialization into cxx_param_decl()
allowing us to get rid of src/sim/sim_object_params.hh.  Now the
generation and wrapping of the base SimObject param struct is more
in line with how derived objects are handled.

--HG--
rename : src/python/swig/sim_object.i => src/python/swig/pyobject.i
2011-10-20 13:09:10 -07:00
Steve Reinhardt
45d14e02c4 scons/swig: refactor some of the scons/SWIG code
- Move the random bits of SWIG code generation out of src/SConscript
  file and into methods on the objects being wrapped.
- Cleaned up some variable naming and added some comments to make
  the process a little clearer.
- Did a little generated file/module renaming:
   - vptype_Foo now Foo_vector
   - init_Foo is now Foo_init
  This makes it easier to see all the Foo-related files in a
  sorted directory listing.
- Made cxx_predecls and swig_predecls normal SimObject classmethods.
- Got rid of swig_objdecls hook, even though this breaks the System
  objects get/setMemoryMode method exports.  Will be fixing this in
  a future changeset.
2011-10-20 13:08:49 -07:00
Nathan Binkert
d8cc8d3ab8 scons: fix building of shared objects 2011-10-17 17:06:40 -07:00
Gabe Black
ca36c01f7e SE/FS: Make some system funcs available in SE and FS. 2011-10-16 05:06:40 -07:00
Gabe Black
464c485d0c SE/FS: Include getMemPort in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
bcf664e5f9 SE/FS: Turn on the page table class in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
6ba3ebae43 SE/FS: Build in the tport in FS mode. 2011-10-16 05:06:40 -07:00
Gabe Black
3595b0c5a1 SE/FS: Build/expose vport in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
79ba4b6595 SPARC: Build vtophys into SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
5ee3f586bf Power: Add a stub implementation for vtophys in SE and FS. 2011-10-16 05:06:39 -07:00
Gabe Black
baae510b56 MIPS: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
1eb459a79e ARM: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
b2af015b97 ARM: Turn on the page table walker on ARM in SE mode. 2011-10-16 05:06:38 -07:00
Gabe Black
dd8fed7387 Alpha: Turn on vtophys in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
e8e9f97312 CPU: Make physPort and getPhysPort available in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
85ca77d114 X86: Build vtophys in SE mode. 2011-10-13 02:26:21 -07:00
Gabe Black
8adc6781bf X86: Turn on the page table walker in SE mode. 2011-10-13 02:22:23 -07:00
Gabe Black
4b2e5ebead SPARC: Remove the last checks of FULL_SYSTEM. 2011-10-13 01:37:19 -07:00
Gabe Black
6b5ede5e39 SPARC: Narrow the scope of #if FULL_SYSTEM in SPARC's faults. 2011-10-13 01:11:00 -07:00
Nilay Vaish
b61e34fab8 mc146818: Correctly serialize tickEvent
'tickEvent' was not being serialized as in its place 'event' was being used.
This patch rectifies this error.
2011-10-10 17:01:33 -05:00
Gabe Black
afa7a34563 SPARC: Let the TLB have friends in FS mode. 2011-10-10 00:38:57 -07:00
Gabe Black
8eec565d0d SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC. 2011-10-10 00:31:51 -07:00
Gabe Black
5bab52d56d [mq]: sefssparcregfile.patch 2011-10-09 23:48:27 -07:00
Gabe Black
48b40cff65 Interrupts: Make the IO APIC go get the local APICs.
This is so they don't have to declare themselves to the IO APIC and don't have
to have a pointer to the platform object.
2011-10-09 04:44:02 -07:00
Gabe Black
f338d60930 SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
Gabe Black
bfec60ad3a Ports: Print the port name when a port is used but not attached to anything. 2011-10-08 23:24:32 -07:00
Gabe Black
d368344092 SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
2011-10-04 02:26:03 -07:00
Gabe Black
e2dbe59f5d SE/FS: Remove System::platform and Platform::intrFrequency.
In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.

This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.

After this change, a platform will need to have a system, but a system won't
have to have a platform.
2011-09-30 00:29:07 -07:00
Gabe Black
91dd72a99a X86: Remove FULL_SYSTEM from the x86 faults. 2011-09-30 00:28:40 -07:00
Gabe Black
51f7a66660 SE/FS: Build the devices in SE mode. 2011-09-30 00:28:33 -07:00
Gabe Black
35e20c7470 SE/FS: Use the new FullSystem constant where possible. 2011-09-30 00:27:16 -07:00
Gabe Black
4fcf8e9959 O3: Tidy up some DPRINTFs in the LSQ. 2011-09-27 00:25:26 -07:00
Gabe Black
44ed4849d4 Faults: Replace calls to genMachineCheckFault with M5PanicFault. 2011-09-27 00:24:43 -07:00
Gabe Black
2ed3eef9b0 Faults: Add in generic faults that work like panics, warns, etc.
These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
2011-09-27 00:17:09 -07:00
Gabe Black
ea79850f90 Faults: Make the generic faults more consistent between SE and FS.
All of the classes will now be available in both modes, and only
GenericPageTableFault will continue to check the mode for conditional
compilation. It uses a process object to handle the fault in SE mode, and
for now those aren't available in FS mode.
2011-09-27 00:16:33 -07:00
Gabe Black
997cbe1c09 ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
2011-09-26 23:48:54 -07:00
Nilay Vaish
56bddab189 LSQ: Moved a couple of lines to enable O3 + Ruby
This patch makes O3 CPU work along with the Ruby memory model. Ruby
overwrites the senderState pointer with another pointer. The pointer
is restored only when Ruby gets done with the packet. LSQ makes use of
senderState just after sendTiming() returns. But the dynamic_cast returns
a NULL pointer since Ruby's senderState pointer is from a different class.
Storing the senderState pointer before calling sendTiming() does away with
the problem.
2011-09-26 12:18:32 -05:00
Gabe Black
16e0215d30 SE/FS: Define a const bool FullSystem which will equal FULL_SYSTEM.
This constant will have the same value as FULL_SYSTEM but will not be usable
by the preprocessor. It can be substituted into places where FULL_SYSTEM is
used in a C++ context and will make it easier to find which parts of the
simulator still use FULL_SYSTEM with the preprocessor using grep.
2011-09-26 02:09:04 -07:00
Gabe Black
7770239792 SCons: Add a comment I forgot to add in earlier.
This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
2011-09-24 17:03:18 -07:00
Gabe Black
9f26aaa7d7 SCons: Make the ISA parser a source for its output files like the comments say.
There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
2011-09-24 16:59:11 -07:00
Gabe Black
40b6c9cb2e X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
2011-09-23 02:42:22 -07:00
Steve Reinhardt
84f0a1bd91 event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor.  I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
2011-09-22 18:59:55 -07:00
Steve Reinhardt
ba79155d9d pseudo_inst: clean up workbegin/workend functions
Use exitSimLoop() function instead of explicitly scheduling
on mainEventQueue (which won't work once we go to multiple
event queues).  Also introduced a local params variable to
shorten a lot of expressions.
2011-09-22 18:59:54 -07:00
Steve Reinhardt
4a4bc2e18b params.py: enhance IpAddress param handling
Print IpAddress params in dot notation for readability.
Properly compare IpAddress objects (by value and not object identity).
Also fix up derived param classes (IpNetmask and IpWithPort)
similarly.
2011-09-22 18:58:14 -07:00
Gabe Black
9a38dc6194 MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and adds
names for the exception code constants.
2011-09-19 06:17:21 -07:00
Gabe Black
4455fc484d MIPS, faults: Update how the PC is set. 2011-09-19 06:17:21 -07:00
Gabe Black
0d9ee17012 MIPS: Get rid of skipFaultInstruction and setRestartAddress.
Neither of these functions were used.
2011-09-19 06:17:21 -07:00
Gabe Black
5ea09771be MIPS: Use inheritance to consolidate class definitions. 2011-09-19 06:17:21 -07:00
Gabe Black
7d19ff170d MIPS: Always compile in setExceptionState, including in SE mode.
Also fix the newly exposed and preexisting compile errors. This code hasn't
been exposed in a while, and it's not up to date with the rest of gem5.
2011-09-19 06:17:21 -07:00
Gabe Black
48b6636d01 MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of having two
different classes. The classes were also misleadingly named since loads are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I haven't
looked at it closely.
2011-09-19 06:17:20 -07:00
Gabe Black
efcded334c MIPS: Get rid of the unused "count" field in FaultVals. 2011-09-19 06:17:20 -07:00
Gabe Black
ffeab06378 MIPS: Move the genMachineCheckFault function near MachineCheckFault.
Since they're so closely linked, they should be next to each other in the
file.
2011-09-19 06:17:20 -07:00
Gabe Black
59d7fc6b26 MIPS: Consolidate the two AddressErrorFault variants. 2011-09-19 06:17:20 -07:00
Gabe Black
717d4ae930 Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.
These functions aren't called anywhere and are probably only theoretically
useful.
2011-09-19 06:17:20 -07:00
Gabe Black
110c59b414 MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
2011-09-19 06:17:19 -07:00
Gabe Black
7e704c9f51 MIPS: Add constructors to the fault classes. 2011-09-19 06:17:19 -07:00
Gabe Black
27388c0fe0 MIPS: Use the CRTP to streamline the Fault class definitions.
CRTP stands for the curiously recurring template pattern.
2011-09-19 06:17:19 -07:00
Gabe Black
59a5605fff SPARC: Remove #if FULL_SYSTEMs from the ISA description. 2011-09-19 06:17:19 -07:00
Gabe Black
f21ae529fb MIPS: Get rid of #if style config checks in the ISA description. 2011-09-19 06:14:02 -07:00
Gabe Black
4ad36a4684 MIPS: Guard SystemCallFault::invoke consistently.
Make sure it's declared iff it's also defined.
2011-09-19 06:09:15 -07:00
Gabe Black
49967ed268 MIPS: Get rid of the unused (and partially defined) CacheError fault. 2011-09-19 05:53:54 -07:00
Gabe Black
3eca0a2bc9 Endianness: Make it easier to check the compiled in guest endianness.
It was technically possible but clumsy to determine what endianness a guest
was configured with using the state in byteswap.hh. This change makes that
information available more directly.

Also get rid of unused (and mildly redundant) ByteOrderDiffers constant.
2011-09-19 05:19:45 -07:00
Gabe Black
978e41eab0 Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
2011-09-19 03:40:30 -07:00
Gabe Black
44659cb608 PseudoInst: Make all the pseudo insts available in SE and FS. 2011-09-19 03:39:58 -07:00
Gabe Black
7701c5b1ec X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.
The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
2011-09-19 02:53:37 -07:00
Gabe Black
10c2e37f60 Syscall: Make the syscall function available in both SE and FS modes.
In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
2011-09-19 02:46:48 -07:00
Gabe Black
83aa47adca PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts. 2011-09-19 02:40:19 -07:00
Gabe Black
9eda6b1d88 Pseudoinst: Add an initParam pseudo inst function. 2011-09-18 23:26:39 -07:00
Ali Saidi
6caea472a9 IGbE: Clean up debug printing and proprly account for copied bytes.
Some DPRINTFs were printing uninitalized values because the DPRINTFs were
always being printed even when the features they were printing weren't
being used. This change moves the DPRINTFs into the appropriate if blocks
and initializes the state variables correctly.

There also is a case where the offset into the packet could be calculated
incorrectly during a DMA that is fixed.
2011-09-13 12:06:13 -05:00
Daniel Johnson
cbb23a1d3c ARM: update TLB to set request packet ASID field 2011-09-13 12:06:13 -05:00
Daniel Johnson
52d30813ca Mem: Allow ASID to be set after request is created. 2011-09-13 12:06:13 -05:00
Chander Sudanthi
7c479d7349 CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13 12:06:13 -05:00
Daniel Johnson
09a6e424ec ARM: Implement numcpus bits in L2CTLR register. 2011-09-13 12:06:13 -05:00
Ali Saidi
0c29a97ba9 Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
2011-09-13 12:06:13 -05:00
Ali Saidi
649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
Deyuan Guo
bb921b1459 MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
2011-09-10 03:45:25 -07:00
Gabe Black
6a2b223112 PseudoInst: Add compiler guards to pseudo_inst.hh. 2011-09-10 02:31:15 -07:00
Gabe Black
49a7ed0397 StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
2011-09-09 02:40:11 -07:00
Gabe Black
b7b545bc38 Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 02:30:01 -07:00
Gabe Black
a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
Gabe Black
f370ac5c18 ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
Gabe Black
f4dc64655f ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
2011-09-08 03:20:05 -07:00
Gabe Black
87d687e242 X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
2011-09-05 18:36:26 -07:00
Gabe Black
3bd0b9654c X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
2011-09-05 02:48:57 -07:00
Lisa Hsu
365966304e TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why.  Add a little warn() to explain it a bit.  Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-02 17:04:00 -07:00
Lisa Hsu
f6a2ef22ff Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
2011-09-01 15:25:54 -07:00
Lisa Hsu
ae12ae3023 Functional Accesses: Update states to support Broadcast/Snooping protocols.
In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.

Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().
2011-09-01 11:41:44 -07:00