Mem: Add simple bandwidth stats to PhysicalMemory
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010-2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -126,6 +126,65 @@ PhysicalMemory::~PhysicalMemory()
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munmap((char*)pmemAddr, size());
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}
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void
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PhysicalMemory::regStats()
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{
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using namespace Stats;
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bytesRead
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.name(name() + ".bytes_read")
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.desc("Number of bytes read from this memory")
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;
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bytesInstRead
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.name(name() + ".bytes_inst_read")
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.desc("Number of instructions bytes read from this memory")
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;
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bytesWritten
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.name(name() + ".bytes_written")
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.desc("Number of bytes written to this memory")
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;
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numReads
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.name(name() + ".num_reads")
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.desc("Number of read requests responded to by this memory")
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;
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numWrites
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.name(name() + ".num_writes")
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.desc("Number of write requests responded to by this memory")
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;
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numOther
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.name(name() + ".num_other")
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.desc("Number of other requests responded to by this memory")
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;
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bwRead
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.name(name() + ".bw_read")
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.desc("Total read bandwidth from this memory (bytes/s)")
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.precision(0)
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.prereq(bytesRead)
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;
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bwInstRead
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.name(name() + ".bw_inst_read")
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.desc("Instruction read bandwidth from this memory (bytes/s)")
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.precision(0)
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.prereq(bytesInstRead)
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;
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bwWrite
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.name(name() + ".bw_write")
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.desc("Write bandwidth from this memory (bytes/s)")
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.precision(0)
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.prereq(bytesWritten)
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;
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bwTotal
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.name(name() + ".bw_total")
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.desc("Total bandwidth to/from this memory (bytes/s)")
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.precision(0)
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.prereq(bwTotal)
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;
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bwRead = bytesRead / simSeconds;
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bwInstRead = bytesInstRead / simSeconds;
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bwWrite = bytesWritten / simSeconds;
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bwTotal = (bytesRead + bytesWritten) / simSeconds;
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}
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unsigned
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PhysicalMemory::deviceBlockSize() const
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{
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@ -304,6 +363,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt)
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Read/Write");
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numOther++;
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} else if (pkt->isRead()) {
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assert(!pkt->isWrite());
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if (pkt->isLLSC()) {
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@ -312,12 +372,18 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt)
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if (pmemAddr)
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memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
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TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
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numReads++;
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bytesRead += pkt->getSize();
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if (pkt->req->isInstFetch())
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bytesInstRead += pkt->getSize();
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} else if (pkt->isWrite()) {
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if (writeOK(pkt)) {
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if (pmemAddr)
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memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Write");
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numWrites++;
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bytesWritten += pkt->getSize();
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}
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} else if (pkt->isInvalidate()) {
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//upgrade or invalidate
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@ -38,11 +38,13 @@
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#include <string>
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#include "base/range.hh"
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#include "base/statistics.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/tport.hh"
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#include "params/PhysicalMemory.hh"
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#include "sim/eventq.hh"
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#include "sim/stats.hh"
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//
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// Functional model for a contiguous block of physical memory. (i.e. RAM)
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@ -154,6 +156,28 @@ class PhysicalMemory : public MemObject
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uint64_t _size;
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uint64_t _start;
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/** Number of total bytes read from this memory */
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Stats::Scalar bytesRead;
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/** Number of instruction bytes read from this memory */
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Stats::Scalar bytesInstRead;
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/** Number of bytes written to this memory */
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Stats::Scalar bytesWritten;
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/** Number of read requests */
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Stats::Scalar numReads;
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/** Number of write requests */
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Stats::Scalar numWrites;
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/** Number of other requests */
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Stats::Scalar numOther;
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/** Read bandwidth from this memory */
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Stats::Formula bwRead;
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/** Read bandwidth from this memory */
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Stats::Formula bwInstRead;
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/** Write bandwidth from this memory */
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Stats::Formula bwWrite;
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/** Total bandwidth from this memory */
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Stats::Formula bwTotal;
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public:
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uint64_t size() { return _size; }
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uint64_t start() { return _start; }
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@ -182,6 +206,11 @@ class PhysicalMemory : public MemObject
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virtual Tick calculateLatency(PacketPtr pkt);
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public:
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/**
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* Register Statistics
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*/
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void regStats();
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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