From e1c48dfce556ddb5ae2189dd8ef5ef542170b304 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 25 Jan 2012 17:18:25 +0000
Subject: [PATCH] Mem: Add simple bandwidth stats to PhysicalMemory

---
 src/mem/physical.cc | 68 ++++++++++++++++++++++++++++++++++++++++++++-
 src/mem/physical.hh | 29 +++++++++++++++++++
 2 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 8b319940b..a63f6e619 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -126,6 +126,65 @@ PhysicalMemory::~PhysicalMemory()
         munmap((char*)pmemAddr, size());
 }
 
+void
+PhysicalMemory::regStats()
+{
+    using namespace Stats;
+
+    bytesRead
+        .name(name() + ".bytes_read")
+        .desc("Number of bytes read from this memory")
+        ;
+    bytesInstRead
+        .name(name() + ".bytes_inst_read")
+        .desc("Number of instructions bytes read from this memory")
+        ;
+    bytesWritten
+        .name(name() + ".bytes_written")
+        .desc("Number of bytes written to this memory")
+        ;
+    numReads
+        .name(name() + ".num_reads")
+        .desc("Number of read requests responded to by this memory")
+        ;
+    numWrites
+        .name(name() + ".num_writes")
+        .desc("Number of write requests responded to by this memory")
+        ;
+    numOther
+        .name(name() + ".num_other")
+        .desc("Number of other requests responded to by this memory")
+        ;
+    bwRead
+        .name(name() + ".bw_read")
+        .desc("Total read bandwidth from this memory (bytes/s)")
+        .precision(0)
+        .prereq(bytesRead)
+        ;
+    bwInstRead
+        .name(name() + ".bw_inst_read")
+        .desc("Instruction read bandwidth from this memory (bytes/s)")
+        .precision(0)
+        .prereq(bytesInstRead)
+        ;
+    bwWrite
+        .name(name() + ".bw_write")
+        .desc("Write bandwidth from this memory (bytes/s)")
+        .precision(0)
+        .prereq(bytesWritten)
+        ;
+    bwTotal
+        .name(name() + ".bw_total")
+        .desc("Total bandwidth to/from this memory (bytes/s)")
+        .precision(0)
+        .prereq(bwTotal)
+        ;
+    bwRead = bytesRead / simSeconds;
+    bwInstRead = bytesInstRead / simSeconds;
+    bwWrite = bytesWritten / simSeconds;
+    bwTotal = (bytesRead + bytesWritten) / simSeconds;
+}
+
 unsigned
 PhysicalMemory::deviceBlockSize() const
 {
@@ -304,6 +363,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt)
 
         assert(!pkt->req->isInstFetch());
         TRACE_PACKET("Read/Write");
+        numOther++;
     } else if (pkt->isRead()) {
         assert(!pkt->isWrite());
         if (pkt->isLLSC()) {
@@ -312,12 +372,18 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt)
         if (pmemAddr)
             memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
         TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
+        numReads++;
+        bytesRead += pkt->getSize();
+        if (pkt->req->isInstFetch())
+            bytesInstRead += pkt->getSize();
     } else if (pkt->isWrite()) {
         if (writeOK(pkt)) {
             if (pmemAddr)
                 memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
             assert(!pkt->req->isInstFetch());
             TRACE_PACKET("Write");
+            numWrites++;
+            bytesWritten += pkt->getSize();
         }
     } else if (pkt->isInvalidate()) {
         //upgrade or invalidate
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 1e00d8f5b..b447237c7 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -38,11 +38,13 @@
 #include <string>
 
 #include "base/range.hh"
+#include "base/statistics.hh"
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"
 #include "params/PhysicalMemory.hh"
 #include "sim/eventq.hh"
+#include "sim/stats.hh"
 
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
@@ -154,6 +156,28 @@ class PhysicalMemory : public MemObject
 
     uint64_t _size;
     uint64_t _start;
+
+    /** Number of total bytes read from this memory */
+    Stats::Scalar bytesRead;
+    /** Number of instruction bytes read from this memory */
+    Stats::Scalar bytesInstRead;
+    /** Number of bytes written to this memory */
+    Stats::Scalar bytesWritten;
+    /** Number of read requests */
+    Stats::Scalar numReads;
+    /** Number of write requests */
+    Stats::Scalar numWrites;
+    /** Number of other requests */
+    Stats::Scalar numOther;
+    /** Read bandwidth from this memory */
+    Stats::Formula bwRead;
+    /** Read bandwidth from this memory */
+    Stats::Formula bwInstRead;
+    /** Write bandwidth from this memory */
+    Stats::Formula bwWrite;
+    /** Total bandwidth from this memory */
+    Stats::Formula bwTotal;
+
   public:
     uint64_t size() { return _size; }
     uint64_t start() { return _start; }
@@ -182,6 +206,11 @@ class PhysicalMemory : public MemObject
     virtual Tick calculateLatency(PacketPtr pkt);
 
   public:
+     /**
+     * Register Statistics
+     */
+    void regStats();
+
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);