Mrinmoy Ghosh 7e104a1af2 prefetcher: Make prefetcher a sim object instead of it being a parameter on cache		2012-02-12 16:07:38 -06:00
..
arch	SPARC: Make PSTATE and HPSTATE a BitUnion.	2012-02-11 14:16:38 -08:00
base	Merge with head, hopefully the last time for this batch.	2012-01-31 22:40:08 -08:00
cpu	O3 CPU: Improve handling of delayed commit flag	2012-02-10 08:37:31 -06:00
dev	configs: More fixes for the memory system updates	2012-02-01 09:48:28 -08:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	Merge with main repository.	2012-01-30 21:07:57 -08:00
mem	prefetcher: Make prefetcher a sim object instead of it being a parameter on cache	2012-02-12 16:07:38 -06:00
python	Merge with head, hopefully the last time for this batch.	2012-01-31 22:40:08 -08:00
sim	sim/system: initialize the pagePtr variable	2012-02-10 09:52:32 -06:00
unittest	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	clang: Enable compiling gem5 using clang 2.9 and 3.0	2012-01-31 12:05:52 -05:00