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clang: Enable compiling gem5 using clang 2.9 and 3.0

Browse source 
This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.
This commit is contained in:
Koan-Sin Tan 2012-01-31 12:05:52 -05:00
parent 4590b91fb8
commit 7d4f187700
88 changed files with 255 additions and 391 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
SConstruct
View file

@ -473,7 +473,8 @@ CXX_V = readCommand([main['CXX'],'-V'], exception=False)
main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
main['SUNCC'] = CXX_V and CXX_V.find('Sun C++') >= 0
main['ICC'] = CXX_V and CXX_V.find('Intel') >= 0
if main['GCC'] + main['SUNCC'] + main['ICC'] > 1:
main['CLANG'] = CXX_V and CXX_V.find('clang') >= 0
if main['GCC'] + main['SUNCC'] + main['ICC'] + main['CLANG'] > 1:
print 'Error: How can we have two at the same time?'
Exit(1)
@ -501,6 +502,24 @@ elif main['SUNCC']:
main.Append(CCFLAGS=['-library=stlport4'])
main.Append(CCFLAGS=['-xar'])
#main.Append(CCFLAGS=['-instances=semiexplicit'])
elif main['CLANG']:
clang_version_re = re.compile(".* version (\d+\.\d+)")
clang_version_match = clang_version_re.match(CXX_version)
if (clang_version_match):
clang_version = clang_version_match.groups()[0]
if compareVersions(clang_version, "2.9") < 0:
print 'Error: clang version 2.9 or newer required.'
print ' Installed version:', clang_version
Exit(1)
else:
print 'Error: Unable to determine clang version.'
Exit(1)
main.Append(CCFLAGS=['-pipe'])
main.Append(CCFLAGS=['-fno-strict-aliasing'])
main.Append(CCFLAGS=['-Wall', '-Wno-sign-compare', '-Wundef'])
main.Append(CCFLAGS=['-Wno-tautological-compare'])
main.Append(CCFLAGS=['-Wno-self-assign'])
else:
print 'Error: Don\'t know what compiler options to use for your compiler.'
print ' Please fix SConstruct and src/SConscript and try again.'

2
ext/libelf/SConscript
View file

@ -94,6 +94,8 @@ if m4env['GCC']:
major,minor,dot = [int(x) for x in m4env['GCC_VERSION'].split('.')]
if major >= 4:
m4env.Append(CCFLAGS=['-Wno-pointer-sign'])
if m4env['CLANG']:
m4env.Append(CCFLAGS=['-Wno-initializer-overrides', '-Wno-pointer-sign'])
m4env.Append(CCFLAGS=['-Wno-implicit'])
del m4env['CPPPATH']

5
src/SConscript
View file

@ -854,6 +854,9 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
swig_env.Append(CCFLAGS='-Wno-unused-label')
if compareVersions(env['GCC_VERSION'], '4.6.0') != -1:
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
if env['CLANG']:
swig_env.Append(CCFLAGS=['-Wno-unused-label'])
werror_env = new_env.Clone()
werror_env.Append(CCFLAGS='-Werror')
@ -928,7 +931,7 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
# Debug binary
ccflags = {}
if env['GCC']:
if env['GCC'] or env['CLANG']:
if sys.platform == 'sunos5':
ccflags['debug'] = '-gstabs+'
else:

4
src/arch/alpha/tlb.cc
View file

@ -63,7 +63,7 @@ TLB::TLB(const Params *p)
: BaseTLB(p), size(p->size), nlu(0)
{
table = new TlbEntry[size];
memset(table, 0, sizeof(TlbEntry[size]));
memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
}
@ -279,7 +279,7 @@ void
TLB::flushAll()
{
DPRINTF(TLB, "flushAll\n");
memset(table, 0, sizeof(TlbEntry[size]));
memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
lookupTable.clear();
nlu = 0;

2
src/arch/alpha/tlb.hh
View file

@ -49,7 +49,7 @@ class ThreadContext;
namespace AlphaISA {
class TlbEntry;
struct TlbEntry;
class TLB : public BaseTLB
{

1
src/arch/arm/insts/static_inst.hh
View file

@ -46,6 +46,7 @@
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "sim/byteswap.hh"
namespace ArmISA
{

3
src/arch/arm/insts/vfp.hh
View file

@ -107,6 +107,9 @@ enum VfpRoundingMode
VfpRoundZero = 3
};
static inline float bitsToFp(uint64_t, float);
static inline uint32_t fpToBits(float);
template <class fpType>
static inline bool
flushToZero(fpType &op)

2
src/arch/arm/isa/templates/basic.isa
View file

@ -49,7 +49,7 @@ def template BasicDeclare {{
// Basic instruction class constructor template.
def template BasicConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
%(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {

2
src/arch/arm/miscregs.cc
View file

@ -411,7 +411,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
}
break;
case 11:
if (opc1 >= 0 && opc1 <=7) {
if (opc1 <=7) {
switch (crm) {
case 0:
case 1:

4
src/arch/generic/memhelpers.hh
View file

@ -64,7 +64,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
memset(&mem, 0, sizeof(mem));
Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
if (fault == NoFault) {
mem = gtoh(mem);
mem = TheISA::gtoh(mem);
if (traceData)
traceData->setData(mem);
}
@ -92,7 +92,7 @@ writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
{
Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
if (fault == NoFault && res != NULL) {
*res = gtoh((MemT)*res);
*res = TheISA::gtoh((MemT)*res);
}
return fault;
}

2
src/arch/mips/faults.cc
View file

@ -98,7 +98,7 @@ template <> FaultVals MipsFault<TlbInvalidFault>::vals =
template <> FaultVals MipsFault<TlbRefillFault>::vals =
{ "TLB Refill Exception", 0x180, ExcCodeDummy };
template <> FaultVals MipsFault<TlbModifiedFault>::vals =
template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
{ "TLB Modified Exception", 0x180, ExcCodeMod };
void

2
src/arch/mips/faults.hh
View file

@ -299,7 +299,7 @@ class TlbModifiedFault : public TlbFault<TlbModifiedFault>
TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
{}
ExcCode code() const { return vals.code; }
ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); }
};
} // namespace MipsISA

8
src/arch/x86/bios/acpi.hh
View file

@ -48,11 +48,11 @@
class Port;
class X86ACPIRSDPParams;
struct X86ACPIRSDPParams;
class X86ACPISysDescTableParams;
class X86ACPIRSDTParams;
class X86ACPIXSDTParams;
struct X86ACPISysDescTableParams;
struct X86ACPIRSDTParams;
struct X86ACPIXSDTParams;
namespace X86ISA
{

2
src/arch/x86/bios/intelmp.cc
View file

@ -72,7 +72,7 @@ template<class T>
uint8_t
writeOutField(PortProxy* proxy, Addr addr, T val)
{
T guestVal = X86ISA::htog(val);
uint64_t guestVal = X86ISA::htog(val);
proxy->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
uint8_t checkSum = 0;

24
src/arch/x86/bios/intelmp.hh
View file

@ -54,24 +54,24 @@
class PortProxy;
// Config entry types
class X86IntelMPBaseConfigEntryParams;
class X86IntelMPExtConfigEntryParams;
struct X86IntelMPBaseConfigEntryParams;
struct X86IntelMPExtConfigEntryParams;
// General table structures
class X86IntelMPConfigTableParams;
class X86IntelMPFloatingPointerParams;
struct X86IntelMPConfigTableParams;
struct X86IntelMPFloatingPointerParams;
// Base entry types
class X86IntelMPBusParams;
class X86IntelMPIOAPICParams;
class X86IntelMPIOIntAssignmentParams;
class X86IntelMPLocalIntAssignmentParams;
class X86IntelMPProcessorParams;
struct X86IntelMPBusParams;
struct X86IntelMPIOAPICParams;
struct X86IntelMPIOIntAssignmentParams;
struct X86IntelMPLocalIntAssignmentParams;
struct X86IntelMPProcessorParams;
// Extended entry types
class X86IntelMPAddrSpaceMappingParams;
class X86IntelMPBusHierarchyParams;
class X86IntelMPCompatAddrSpaceModParams;
struct X86IntelMPAddrSpaceMappingParams;
struct X86IntelMPBusHierarchyParams;
struct X86IntelMPCompatAddrSpaceModParams;
namespace X86ISA
{

6
src/arch/x86/bios/smbios.hh
View file

@ -52,9 +52,9 @@
#include "sim/sim_object.hh"
class PortProxy;
class X86SMBiosBiosInformationParams;
class X86SMBiosSMBiosStructureParams;
class X86SMBiosSMBiosTableParams;
struct X86SMBiosBiosInformationParams;
struct X86SMBiosSMBiosStructureParams;
struct X86SMBiosSMBiosTableParams;
namespace X86ISA
{

4
src/base/fast_alloc.cc
View file

@ -40,10 +40,6 @@
#if USE_FAST_ALLOC
#ifdef __GNUC__
#pragma implementation
#endif
void *FastAlloc::freeLists[Num_Buckets];
#if FAST_ALLOC_STATS

2
src/base/range_map.hh
View file

@ -215,7 +215,7 @@ class range_multimap
{
std::pair<iterator,iterator> p;
p = find(r);
if (p.first->first.start == r.start && p.first->first.end == r.end ||
if ((p.first->first.start == r.start && p.first->first.end == r.end) ||
p.first == tree.end())
return tree.insert(std::make_pair<Range<T>,V>(r, d));
else

2
src/base/remote_gdb.hh
View file

@ -204,7 +204,7 @@ class BaseRemoteGDB
public:
HardBreakpoint(BaseRemoteGDB *_gdb, Addr addr);
std::string name() { return gdb->name() + ".hwbkpt"; }
const std::string name() const { return gdb->name() + ".hwbkpt"; }
virtual void process(ThreadContext *tc);
};

4
src/base/stl_helpers.hh
View file

@ -72,7 +72,7 @@ class ContainerPrint
// Treat all objects in an stl container as pointers to heap objects,
// calling delete on each one and zeroing the pointers along the way
template <typename T, template <typename T, typename A> class C, typename A>
template <template <typename T, typename A> class C, typename T, typename A>
void
deletePointers(C<T,A> &container)
{
@ -81,7 +81,7 @@ deletePointers(C<T,A> &container)
// Write out all elements in an stl container as a space separated
// list enclosed in square brackets
template <typename T, template <typename T, typename A> class C, typename A>
template <template <typename T, typename A> class C, typename T, typename A>
std::ostream &
operator<<(std::ostream& out, const C<T,A> &vec)
{

4
src/cpu/base.cc
View file

@ -371,8 +371,10 @@ BaseCPU::switchOut()
}
void
BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
Port *ic = getPort("icache_port");
Port *dc = getPort("dcache_port");
assert(threadContexts.size() == oldCPU->threadContexts.size());
_cpuId = oldCPU->cpuId();

12
src/cpu/base.hh
View file

@ -61,7 +61,7 @@
#include "arch/interrupts.hh"
#endif
class BaseCPUParams;
struct BaseCPUParams;
class BranchPred;
class CheckerCPU;
class ThreadContext;
@ -241,16 +241,16 @@ class BaseCPU : public MemObject
/// Notify the CPU that the indicated context is now active. The
/// delay parameter indicates the number of ticks to wait before
/// executing (typically 0 or 1).
virtual void activateContext(int thread_num, int delay) {}
virtual void activateContext(ThreadID thread_num, int delay) {}
/// Notify the CPU that the indicated context is now suspended.
virtual void suspendContext(int thread_num) {}
virtual void suspendContext(ThreadID thread_num) {}
/// Notify the CPU that the indicated context is now deallocated.
virtual void deallocateContext(int thread_num) {}
virtual void deallocateContext(ThreadID thread_num) {}
/// Notify the CPU that the indicated context is now halted.
virtual void haltContext(int thread_num) {}
virtual void haltContext(ThreadID thread_num) {}
/// Given a Thread Context pointer return the thread num
int findContext(ThreadContext *tc);
@ -279,7 +279,7 @@ class BaseCPU : public MemObject
/// Take over execution from the given CPU. Used for warm-up and
/// sampling.
virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
virtual void takeOverFrom(BaseCPU *);
/**
* Number of threads we're actually simulating (<= SMT_MAX_THREADS).

6
src/cpu/func_unit.hh
View file

@ -47,8 +47,9 @@
//
//
struct OpDesc : public SimObject
class OpDesc : public SimObject
{
public:
OpClass opClass;
unsigned opLat;
unsigned issueLat;
@ -58,8 +59,9 @@ struct OpDesc : public SimObject
issueLat(p->issueLat) {};
};
struct FUDesc : public SimObject
class FUDesc : public SimObject
{
public:
std::vector<OpDesc *> opDescList;
unsigned number;

12
src/cpu/inorder/cpu.cc
View file

@ -83,7 +83,7 @@ InOrderCPU::TickEvent::process()
const char *
InOrderCPU::TickEvent::description()
InOrderCPU::TickEvent::description() const
{
return "InOrderCPU tick event";
}
@ -168,7 +168,7 @@ InOrderCPU::CPUEvent::process()
const char *
InOrderCPU::CPUEvent::description()
InOrderCPU::CPUEvent::description() const
{
return "InOrderCPU event";
}
@ -1168,11 +1168,11 @@ InOrderCPU::activateNextReadyContext(int delay)
}
void
InOrderCPU::haltContext(ThreadID tid, int delay)
InOrderCPU::haltContext(ThreadID tid)
{
DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
activityRec.activity();
}
@ -1193,9 +1193,9 @@ InOrderCPU::haltThread(ThreadID tid)
}
void
InOrderCPU::suspendContext(ThreadID tid, int delay)
InOrderCPU::suspendContext(ThreadID tid)
{
scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
}
void

8
src/cpu/inorder/cpu.hh
View file

@ -148,7 +148,7 @@ class InOrderCPU : public BaseCPU
void process();
/** Returns the description of the tick event. */
const char *description();
const char *description() const;
};
/** The tick event used for scheduling CPU ticks. */
@ -230,7 +230,7 @@ class InOrderCPU : public BaseCPU
void process();
/** Returns the description of the CPU event. */
const char *description();
const char *description() const;
/** Schedule Event */
void scheduleEvent(int delay);
@ -472,13 +472,13 @@ class InOrderCPU : public BaseCPU
void deactivateThread(ThreadID tid);
/** Schedule a thread suspension on the CPU */
void suspendContext(ThreadID tid, int delay = 0);
void suspendContext(ThreadID tid);
/** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
void suspendThread(ThreadID tid);
/** Schedule a thread halt on the CPU */
void haltContext(ThreadID tid, int delay = 0);
void haltContext(ThreadID tid);
/** Halt Thread, Remove from Active Thread List, Place Thread on Halted
* Threads List

2
src/cpu/inorder/resource.cc
View file

@ -512,7 +512,7 @@ ResourceEvent::process()
}
const char *
ResourceEvent::description()
ResourceEvent::description() const
{
string desc = resource->name() + "-event:slot[" + to_string(slotIdx)
+ "]";

12
src/cpu/inorder/resource.hh
View file

@ -51,6 +51,9 @@ class ResourceRequest;
typedef ResourceRequest ResReq;
typedef ResourceRequest* ResReqPtr;
class CacheRequest;
typedef CacheRequest* CacheReqPtr;
class Resource {
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
@ -154,8 +157,9 @@ class Resource {
* if instruction is actually in resource before
* trying to do access.Needs to be defined for derived units.
*/
virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
{ panic("doCacheAccess undefined for %s", name()); return NoFault; }
virtual void doCacheAccess(DynInstPtr inst, uint64_t *write_result = NULL,
CacheReqPtr split_req = NULL)
{ panic("doCacheAccess undefined for %s", name()); }
/** Setup Squash to be sent out to pipeline and resource pool */
void setupSquash(DynInstPtr inst, int stage_num, ThreadID tid);
@ -283,7 +287,7 @@ class ResourceEvent : public Event
virtual void process();
/** Returns the description of the resource event. */
const char *description();
const char *description() const;
/** Set slot idx for event */
void setSlot(int slot) { slotIdx = slot; }
@ -320,7 +324,7 @@ class ResourceRequest
int reqID;
virtual void setRequest(DynInstPtr _inst, int stage_num,
void setRequest(DynInstPtr _inst, int stage_num,
int res_idx, int slot_num, unsigned _cmd);
virtual void clearRequest();

2
src/cpu/inorder/resource_pool.cc
View file

@ -485,7 +485,7 @@ ResourcePool::ResPoolEvent::process()
const char *
ResourcePool::ResPoolEvent::description()
ResourcePool::ResPoolEvent::description() const
{
return "Resource Pool event";
}

2
src/cpu/inorder/resource_pool.hh
View file

@ -118,7 +118,7 @@ class ResourcePool {
void process();
/** Returns the description of the resource event. */
const char *description();
const char *description() const;
/** Schedule Event */
void scheduleEvent(int delay);

3
src/cpu/inorder/resources/cache_unit.hh
View file

@ -49,9 +49,6 @@
#include "params/InOrderCPU.hh"
#include "sim/sim_object.hh"
class CacheRequest;
typedef CacheRequest* CacheReqPtr;
class CacheReqPacket;
typedef CacheReqPacket* CacheReqPktPtr;

4
src/cpu/inorder/thread_context.cc
View file

@ -131,7 +131,7 @@ InOrderThreadContext::suspend(int delay)
return;
thread->setStatus(ThreadContext::Suspended);
cpu->suspendContext(thread->threadId(), delay);
cpu->suspendContext(thread->threadId());
}
void
@ -144,7 +144,7 @@ InOrderThreadContext::halt(int delay)
return;
thread->setStatus(ThreadContext::Halted);
cpu->haltContext(thread->threadId(), delay);
cpu->haltContext(thread->threadId());
}

2
src/cpu/nativetrace.hh
View file

@ -108,7 +108,7 @@ class NativeTrace : public ExeTracer
{
size_t soFar = 0;
while (soFar < size) {
size_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
ssize_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
if (res < 0)
panic("Read call failed! %s\n", strerror(errno));
else

2
src/cpu/o3/bpred_unit.hh
View file

@ -41,7 +41,7 @@
#include "cpu/pred/tournament.hh"
#include "cpu/inst_seq.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
/**
* Basically a wrapper class to hold both the branch predictor

4
src/cpu/o3/commit.hh
View file

@ -51,10 +51,10 @@
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
template <class>
class O3ThreadState;
struct O3ThreadState;
/**
* DefaultCommit handles single threaded and SMT commit. Its width is

11
src/cpu/o3/cpu.cc
View file

@ -76,7 +76,7 @@
#include "debug/Activity.hh"
#endif
class BaseCPUParams;
struct BaseCPUParams;
using namespace TheISA;
using namespace std;
@ -766,7 +766,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
template <class Impl>
bool
FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
int delay)
{
// Schedule removal of thread data from CPU
if (delay){
@ -787,7 +788,7 @@ void
FullO3CPU<Impl>::suspendContext(ThreadID tid)
{
DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
bool deallocated = deallocateContext(tid, false, 1);
bool deallocated = scheduleDeallocateContext(tid, false, 1);
// If this was the last thread then unschedule the tick event.
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
@ -804,7 +805,7 @@ FullO3CPU<Impl>::haltContext(ThreadID tid)
{
//For now, this is the same as deallocate
DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
deallocateContext(tid, true, 1);
scheduleDeallocateContext(tid, true, 1);
}
template <class Impl>
@ -1230,7 +1231,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
activityRec.reset();
BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
BaseCPU::takeOverFrom(oldCPU);
fetch.takeOverFrom();
decode.takeOverFrom();

4
src/cpu/o3/cpu.hh
View file

@ -79,7 +79,7 @@ class Checkpoint;
class MemObject;
class Process;
class BaseCPUParams;
struct BaseCPUParams;
class BaseO3CPU : public BaseCPU
{
@ -401,7 +401,7 @@ class FullO3CPU : public BaseO3CPU
/** Remove Thread from Active Threads List &&
* Possibly Remove Thread Context from CPU.
*/
bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.

2
src/cpu/o3/decode.hh
View file

@ -36,7 +36,7 @@
#include "base/statistics.hh"
#include "cpu/timebuf.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
/**
* DefaultDecode class handles both single threaded and SMT

4
src/cpu/o3/decode_impl.hh
View file

@ -38,7 +38,9 @@
#include "debug/Decode.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
using std::list;
template<class Impl>
DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)

2
src/cpu/o3/fetch.hh
View file

@ -56,7 +56,7 @@
#include "mem/port.hh"
#include "sim/eventq.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
/**
* DefaultFetch class handles both single threaded and SMT fetch. Its

2
src/cpu/o3/fu_pool.cc
View file

@ -252,7 +252,7 @@ FUPool::switchOut()
}
void
FUPool::takeOverFrom()
FUPool::takeOver()
{
for (int i = 0; i < numFU; i++) {
unitBusy[i] = false;

3
src/cpu/o3/fu_pool.hh
View file

@ -37,7 +37,6 @@
#include <vector>
#include "cpu/op_class.hh"
#include "cpu/sched_list.hh"
#include "params/FUPool.hh"
#include "sim/sim_object.hh"
@ -162,7 +161,7 @@ class FUPool : public SimObject
void switchOut();
/** Takes over from another CPU's thread. */
void takeOverFrom();
void takeOver();
};
#endif // __CPU_O3_FU_POOL_HH__

5
src/cpu/o3/iew.hh
View file

@ -54,7 +54,7 @@
#include "cpu/timebuf.hh"
#include "debug/IEW.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
class FUPool;
/**
@ -94,9 +94,6 @@ class DefaultIEW
typedef typename CPUPol::RenameStruct RenameStruct;
typedef typename CPUPol::IssueStruct IssueStruct;
friend class Impl::O3CPU;
friend class CPUPol::IQ;
public:
/** Overall IEW stage status. Used to determine if the CPU can
* deschedule itself due to a lack of activity.

2
src/cpu/o3/iew_impl.hh
View file

@ -412,7 +412,7 @@ DefaultIEW<Impl>::takeOverFrom()
instQueue.takeOverFrom();
ldstQueue.takeOverFrom();
fuPool->takeOverFrom();
fuPool->takeOver();
initStage();
cpu->activityThisCycle();

4
src/cpu/o3/inst_queue.hh
View file

@ -56,7 +56,7 @@
#include "cpu/timebuf.hh"
#include "sim/eventq.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
class FUPool;
class MemInterface;
@ -93,8 +93,6 @@ class InstructionQueue
// Typedef of iterator through the list of instructions.
typedef typename std::list<DynInstPtr>::iterator ListIt;
friend class Impl::O3CPU;
/** FU completion event class. */
class FUCompletion : public Event {
private:

4
src/cpu/o3/inst_queue_impl.hh
View file

@ -51,7 +51,9 @@
#include "params/DerivO3CPU.hh"
#include "sim/core.hh"
using namespace std;
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
using std::list;
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,

2
src/cpu/o3/lsq.hh
View file

@ -52,7 +52,7 @@
#include "mem/port.hh"
#include "sim/sim_object.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
template <class Impl>
class LSQ {

2
src/cpu/o3/lsq_unit.hh
View file

@ -52,7 +52,7 @@
#include "mem/packet.hh"
#include "mem/port.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
/**
* Class that implements the actual LQ and SQ for each specific

8
src/cpu/o3/mem_dep_unit.cc
View file

@ -32,10 +32,6 @@
#include "cpu/o3/mem_dep_unit_impl.hh"
#include "cpu/o3/store_set.hh"
// Force instantation of memory dependency unit using store sets and
// O3CPUImpl.
template class MemDepUnit<StoreSet, O3CPUImpl>;
#ifdef DEBUG
template <>
int
@ -47,3 +43,7 @@ template <>
int
MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
#endif
// Force instantation of memory dependency unit using store sets and
// O3CPUImpl.
template class MemDepUnit<StoreSet, O3CPUImpl>;

2
src/cpu/o3/mem_dep_unit.hh
View file

@ -49,7 +49,7 @@ struct SNHash {
}
};
class DerivO3CPUParams;
struct DerivO3CPUParams;
template <class Impl>
class InstructionQueue;

2
src/cpu/o3/rename.hh
View file

@ -37,7 +37,7 @@
#include "config/the_isa.hh"
#include "cpu/timebuf.hh"
class DerivO3CPUParams;
struct DerivO3CPUParams;
/**
* DefaultRename handles both single threaded and SMT rename. Its

3
src/cpu/o3/sat_counter.hh
View file

@ -65,7 +65,8 @@ class SatCounter
* @param initial_val Starting value for each counter.
*/
SatCounter(unsigned bits, uint8_t initial_val)
: initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
: initialVal(initial_val), maxVal((1 << bits) - 1),
counter(initial_val)
{
// Check to make sure initial value doesn't exceed the max
// counter value.

3
src/cpu/quiesce_event.hh
View file

@ -36,8 +36,9 @@
class ThreadContext;
/** Event for timing out quiesce instruction */
struct EndQuiesceEvent : public Event
class EndQuiesceEvent : public Event
{
public:
/** A pointer to the thread context that is quiesced */
ThreadContext *tc;

180
src/cpu/sched_list.hh
View file

@ -1,180 +0,0 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Raasch
*/
#ifndef SCHED_LIST_HH
#define SCHED_LIST_HH
#include <list>
#include "base/intmath.hh"
#include "base/misc.hh"
// Any types you use this class for must be covered here...
namespace {
void ClearEntry(int &i) { i = 0; };
void ClearEntry(unsigned &i) { i = 0; };
void ClearEntry(double &i) { i = 0; };
template <class T> void ClearEntry(std::list<T> &l) { l.clear(); };
};
//
// this is a special list type that allows the user to insert elements at a
// specified positive offset from the "current" element, but only allow them
// be extracted from the "current" element
//
template <class T>
class SchedList
{
T *data_array;
unsigned position;
unsigned size;
unsigned mask;
public:
SchedList(unsigned size);
SchedList(void);
void init(unsigned size);
T &operator[](unsigned offset);
void advance(void);
void clear(void);
};
//
// Constructor
//
template<class T>
SchedList<T>::SchedList(unsigned _size)
{
size = _size;
// size must be a power of two
if (!isPowerOf2(size)) {
panic("SchedList: size must be a power of two");
}
if (size < 2) {
panic("SchedList: you don't want a list that small");
}
// calculate the bit mask for the modulo operation
mask = size - 1;
data_array = new T[size];
if (!data_array) {
panic("SchedList: could not allocate memory");
}
clear();
}
template<class T>
SchedList<T>::SchedList(void)
{
data_array = 0;
size = 0;
}
template<class T> void
SchedList<T>::init(unsigned _size)
{
size = _size;
if (!data_array) {
// size must be a power of two
if (size & (size-1)) {
panic("SchedList: size must be a power of two");
}
if (size < 2) {
panic("SchedList: you don't want a list that small");
}
// calculate the bit mask for the modulo operation
mask = size - 1;
data_array = new T[size];
if (!data_array) {
panic("SchedList: could not allocate memory");
}
clear();
}
}
template<class T> void
SchedList<T>::advance(void)
{
ClearEntry(data_array[position]);
// position = (++position % size);
position = ++position & mask;
}
template<class T> void
SchedList<T>::clear(void)
{
for (unsigned i=0; i<size; ++i) {
ClearEntry(data_array[i]);
}
position = 0;
}
template<class T> T&
SchedList<T>::operator[](unsigned offset)
{
if (offset >= size) {
panic("SchedList: can't access element beyond current pointer");
}
// unsigned p = (position + offset) % size;
unsigned p = (position + offset) & mask;
return data_array[p];
}
#endif

6
src/cpu/simple/atomic.cc
View file

@ -174,7 +174,7 @@ AtomicSimpleCPU::switchOut()
void
AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
BaseCPU::takeOverFrom(oldCPU);
assert(!tickEvent.scheduled());
@ -200,7 +200,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
void
AtomicSimpleCPU::activateContext(int thread_num, int delay)
AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay)
{
DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
@ -220,7 +220,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
void
AtomicSimpleCPU::suspendContext(int thread_num)
AtomicSimpleCPU::suspendContext(ThreadID thread_num)
{
DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);

4
src/cpu/simple/atomic.hh
View file

@ -112,8 +112,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
virtual void activateContext(ThreadID thread_num, int delay);
virtual void suspendContext(ThreadID thread_num);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);

4
src/cpu/simple/base.cc
View file

@ -139,7 +139,7 @@ BaseSimpleCPU::~BaseSimpleCPU()
}
void
BaseSimpleCPU::deallocateContext(int thread_num)
BaseSimpleCPU::deallocateContext(ThreadID thread_num)
{
// for now, these are equivalent
suspendContext(thread_num);
@ -147,7 +147,7 @@ BaseSimpleCPU::deallocateContext(int thread_num)
void
BaseSimpleCPU::haltContext(int thread_num)
BaseSimpleCPU::haltContext(ThreadID thread_num)
{
// for now, these are equivalent
suspendContext(thread_num);

6
src/cpu/simple/base.hh
View file

@ -92,7 +92,7 @@ namespace Trace {
class InstRecord;
}
class BaseSimpleCPUParams;
struct BaseSimpleCPUParams;
class BaseSimpleCPU : public BaseCPU
@ -189,8 +189,8 @@ class BaseSimpleCPU : public BaseCPU
void postExecute();
void advancePC(Fault fault);
virtual void deallocateContext(int thread_num);
virtual void haltContext(int thread_num);
virtual void deallocateContext(ThreadID thread_num);
virtual void haltContext(ThreadID thread_num);
// statistics
virtual void regStats();

6
src/cpu/simple/timing.cc
View file

@ -176,7 +176,7 @@ TimingSimpleCPU::switchOut()
void
TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
BaseCPU::takeOverFrom(oldCPU);
// if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
@ -197,7 +197,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
void
TimingSimpleCPU::activateContext(int thread_num, int delay)
TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
{
DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
@ -215,7 +215,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
void
TimingSimpleCPU::suspendContext(int thread_num)
TimingSimpleCPU::suspendContext(ThreadID thread_num)
{
DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);

4
src/cpu/simple/timing.hh
View file

@ -244,8 +244,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
virtual void activateContext(ThreadID thread_num, int delay);
virtual void suspendContext(ThreadID thread_num);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);

2
src/cpu/static_inst.hh
View file

@ -52,7 +52,7 @@ class ThreadContext;
class DynInst;
class Packet;
class O3CPUImpl;
struct O3CPUImpl;
template <class Impl> class BaseO3DynInst;
typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
template <class Impl> class OzoneDynInst;

1
src/dev/alpha/tsunami_cchip.cc
View file

@ -53,7 +53,6 @@
#include "params/TsunamiCChip.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;

6
src/dev/alpha/tsunami_io.cc
View file

@ -54,7 +54,11 @@
#include "mem/port.hh"
#include "sim/system.hh"
using namespace std;
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
using std::string;
using std::ostream;
//Should this be AlphaISA?
using namespace TheISA;

9
src/dev/arm/pl111.cc
View file

@ -50,6 +50,10 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
using std::vector;
using namespace AmbaDev;
// initialize clcd registers
@ -69,11 +73,12 @@ Pl111::Pl111(const Params *p)
pic = simout.create(csprintf("%s.framebuffer.bmp", sys->name()), true);
dmaBuffer = new uint8_t[LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t)];
const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
dmaBuffer = new uint8_t[buffer_size];
memset(lcdPalette, 0, sizeof(lcdPalette));
memset(cursorImage, 0, sizeof(cursorImage));
memset(dmaBuffer, 0, sizeof(dmaBuffer));
memset(dmaBuffer, 0, buffer_size);
if (vncserver)
vncserver->setFramebufferAddr(dmaBuffer);

4
src/dev/arm/pl111.hh
View file

@ -53,8 +53,6 @@
#include "params/Pl111.hh"
#include "sim/serialize.hh"
using namespace std;
class Gic;
class VncServer;
class Bitmap;
@ -304,7 +302,7 @@ class Pl111: public AmbaDmaDevice
EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
/** DMA done event */
vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
std::vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
/** Wrapper to create an event out of the interrupt */
EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;

1
src/dev/copy_engine.cc
View file

@ -45,7 +45,6 @@
#include "sim/system.hh"
using namespace CopyEngineReg;
using namespace std;
CopyEngine::CopyEngine(const Params *p)
: PciDev(p)

6
src/dev/disk_image.cc
View file

@ -170,12 +170,12 @@ CowDiskImage::CowDiskImage(const Params *p)
: DiskImage(p), filename(p->image_file), child(p->child), table(NULL)
{
if (filename.empty()) {
init(p->table_size);
initSectorTable(p->table_size);
} else {
if (!open(filename)) {
if (p->read_only)
fatal("could not open read-only file");
init(p->table_size);
initSectorTable(p->table_size);
}
if (!p->read_only)
@ -270,7 +270,7 @@ CowDiskImage::open(const string &file)
}
void
CowDiskImage::init(int hash_size)
CowDiskImage::initSectorTable(int hash_size)
{
table = new SectorTable(hash_size);

2
src/dev/disk_image.hh
View file

@ -121,7 +121,7 @@ class CowDiskImage : public DiskImage
CowDiskImage(const Params *p);
~CowDiskImage();
void init(int hash_size);
void initSectorTable(int hash_size);
bool open(const std::string &file);
void save();
void save(const std::string &file);

5
src/dev/ide_ctrl.cc
View file

@ -32,7 +32,6 @@
#include <string>
#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "debug/IdeCtrl.hh"
#include "dev/ide_ctrl.hh"
@ -42,7 +41,9 @@
#include "params/IdeController.hh"
#include "sim/byteswap.hh"
using namespace std;
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
using std::string;
// Bus master IDE registers
enum BMIRegOffset {

42
src/dev/ns_gige.cc
View file

@ -50,6 +50,12 @@
#include "params/NSGigE.hh"
#include "sim/system.hh"
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
using std::min;
using std::ostream;
using std::string;
const char *NsRxStateStrings[] =
{
"rxIdle",
@ -81,7 +87,6 @@ const char *NsDmaState[] =
"dmaWriteWaiting"
};
using namespace std;
using namespace Net;
using namespace TheISA;
@ -479,12 +484,12 @@ NSGigE::write(PacketPtr pkt)
// all these #if 0's are because i don't THINK the kernel needs to
// have these implemented. if there is a problem relating to one of
// these, you may need to add functionality in.
// grouped together and #if 0'ed to avoid empty if body and make clang happy
#if 0
if (reg & CFGR_TBI_EN) ;
if (reg & CFGR_MODE_1000) ;
if (reg & CFGR_AUTO_1000)
panic("CFGR_AUTO_1000 not implemented!\n");
if (reg & CFGR_PINT_DUPSTS ||
reg & CFGR_PINT_LNKSTS ||
reg & CFGR_PINT_SPDSTS)
@ -494,22 +499,11 @@ NSGigE::write(PacketPtr pkt)
if (reg & CFGR_MRM_DIS) ;
if (reg & CFGR_MWI_DIS) ;
if (reg & CFGR_T64ADDR) ;
// panic("CFGR_T64ADDR is read only register!\n");
if (reg & CFGR_PCI64_DET)
panic("CFGR_PCI64_DET is read only register!\n");
if (reg & CFGR_DATA64_EN) ;
if (reg & CFGR_M64ADDR) ;
if (reg & CFGR_PHY_RST) ;
if (reg & CFGR_PHY_DIS) ;
if (reg & CFGR_EXTSTS_EN)
extstsEnable = true;
else
extstsEnable = false;
if (reg & CFGR_REQALG) ;
if (reg & CFGR_SB) ;
if (reg & CFGR_POW) ;
@ -518,6 +512,20 @@ NSGigE::write(PacketPtr pkt)
if (reg & CFGR_BROM_DIS) ;
if (reg & CFGR_EXT_125) ;
if (reg & CFGR_BEM) ;
if (reg & CFGR_T64ADDR) ;
// panic("CFGR_T64ADDR is read only register!\n");
#endif
if (reg & CFGR_AUTO_1000)
panic("CFGR_AUTO_1000 not implemented!\n");
if (reg & CFGR_PCI64_DET)
panic("CFGR_PCI64_DET is read only register!\n");
if (reg & CFGR_EXTSTS_EN)
extstsEnable = true;
else
extstsEnable = false;
break;
case MEAR:
@ -541,9 +549,13 @@ NSGigE::write(PacketPtr pkt)
eepromClk = reg & MEAR_EECLK;
// since phy is completely faked, MEAR_MD* don't matter
// grouped together and #if 0'ed to avoid empty if body and make clang happy
#if 0
if (reg & MEAR_MDIO) ;
if (reg & MEAR_MDDIR) ;
if (reg & MEAR_MDC) ;
#endif
break;
case PTSCR:

2
src/dev/pciconfigall.cc
View file

@ -43,8 +43,6 @@
#include "params/PciConfigAll.hh"
#include "sim/system.hh"
using namespace std;
PciConfigAll::PciConfigAll(const Params *p)
: PioDevice(p)
{

4
src/dev/pcidev.cc
View file

@ -52,8 +52,6 @@
#include "sim/byteswap.hh"
#include "sim/core.hh"
using namespace std;
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
int funcid, Platform *p)
@ -341,7 +339,7 @@ PciDev::writeConfig(PacketPtr pkt)
}
void
PciDev::serialize(ostream &os)
PciDev::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));

5
src/mem/cache/base.hh vendored
View file

@ -73,6 +73,7 @@ class BaseCache : public MemObject
MSHRQueue_WriteBuffer
};
public:
/**
* Reasons for caches to be blocked.
*/
@ -83,7 +84,6 @@ class BaseCache : public MemObject
NUM_BLOCKED_CAUSES
};
public:
/**
* Reasons for cache to request a bus.
*/
@ -94,7 +94,7 @@ class BaseCache : public MemObject
NUM_REQUEST_CAUSES
};
private:
protected:
class CachePort : public SimpleTimingPort
{
@ -138,7 +138,6 @@ class BaseCache : public MemObject
}
};
public: //Made public so coherence can get at it.
CachePort *cpuSidePort;
CachePort *memSidePort;

2
src/mem/cache/tags/iic.cc vendored
View file

@ -187,7 +187,7 @@ IIC::regStats(const string &name)
.flags(pdf)
;
repl->regStats(name);
repl->regStatsWithSuffix(name);
if (PROFILE_IIC)
setAccess

2
src/mem/cache/tags/iic_repl/gen.cc vendored
View file

@ -184,7 +184,7 @@ GenRepl::add(unsigned long tag_index)
}
void
GenRepl::regStats(const string name)
GenRepl::regStatsWithSuffix(const string name)
{
using namespace Stats;

2
src/mem/cache/tags/iic_repl/gen.hh vendored
View file

@ -209,7 +209,7 @@ class GenRepl : public Repl
* Register statistics.
* @param name The name to prepend to statistic descriptions.
*/
virtual void regStats(const std::string name);
virtual void regStatsWithSuffix(const std::string name);
/**
* Update the tag pointer to when the tag moves.

2
src/mem/cache/tags/iic_repl/repl.hh vendored
View file

@ -102,7 +102,7 @@ class Repl : public SimObject
* Register statistics.
* @param name The name to prepend to statistic descriptions.
*/
virtual void regStats(const std::string name) = 0;
virtual void regStatsWithSuffix(const std::string name) = 0;
/**
* Update the tag pointer to when the tag moves.

2
src/mem/packet.hh
View file

@ -53,7 +53,7 @@
#include "mem/request.hh"
#include "sim/core.hh"
struct Packet;
class Packet;
typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;
typedef std::list<PacketPtr> PacketList;

11
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
View file

@ -104,11 +104,12 @@ GarnetNetwork_d::init()
for (vector<Router_d*>::const_iterator i= m_router_ptr_vector.begin();
i != m_router_ptr_vector.end(); ++i) {
Router_d* router = safe_cast<Router_d*>(*i);
int router_id=fault_model->declare_router(router->get_num_inports(),
router->get_num_outports(),
router->get_vc_per_vnet(),
getBuffersPerDataVC(),
getBuffersPerCtrlVC());
int router_id M5_VAR_USED =
fault_model->declare_router(router->get_num_inports(),
router->get_num_outports(),
router->get_vc_per_vnet(),
getBuffersPerDataVC(),
getBuffersPerCtrlVC());
assert(router_id == router->get_id());
router->printAggregateFaultProbability(cout);
router->printFaultVector(cout);

2
src/mem/ruby/system/Sequencer.hh
View file

@ -41,7 +41,7 @@
class DataBlock;
class CacheMemory;
class RubySequencerParams;
struct RubySequencerParams;
struct SequencerRequest
{

2
src/python/m5/SimObject.py
View file

@ -477,7 +477,7 @@ struct PyObject;
#include <string>
struct EventQueue;
class EventQueue;
''')
for param in params:
param.cxx_predecls(code)

2
src/sim/core.hh
View file

@ -95,7 +95,7 @@ void setClockFrequency(Tick ticksPerSecond);
void setOutputDir(const std::string &dir);
struct Callback;
class Callback;
void registerExitCallback(Callback *callback);
void doExitCleanup();

4
src/sim/process.cc
View file

@ -96,8 +96,8 @@ AuxVector<IntType>::AuxVector(IntType type, IntType val)
a_val = TheISA::htog(val);
}
template class AuxVector<uint32_t>;
template class AuxVector<uint64_t>;
template struct AuxVector<uint32_t>;
template struct AuxVector<uint64_t>;
Process::Process(ProcessParams * params)
: SimObject(params), system(params->system),

4
src/sim/process.hh
View file

@ -52,8 +52,8 @@
#include "sim/syscallreturn.hh"
class PageTable;
class ProcessParams;
class LiveProcessParams;
struct ProcessParams;
struct LiveProcessParams;
class SyscallDesc;
class System;
class ThreadContext;

2
src/sim/process_impl.hh
View file

@ -56,7 +56,7 @@ copyStringArray(std::vector<std::string> &strings,
{
AddrType data_ptr_swap;
for (std::vector<std::string>::size_type i = 0; i < strings.size(); ++i) {
data_ptr_swap = htog(data_ptr);
data_ptr_swap = TheISA::htog(data_ptr);
memProxy->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap,
sizeof(AddrType));
memProxy->writeString(data_ptr, strings[i].c_str());

7
src/sim/serialize.cc
View file

@ -438,7 +438,7 @@ class Globals : public Serializable
public:
const string name() const;
void serialize(ostream &os);
void unserialize(Checkpoint *cp);
void unserialize(Checkpoint *cp, const std::string &section);
};
/// The one and only instance of the Globals class.
@ -461,9 +461,8 @@ Globals::serialize(ostream &os)
}
void
Globals::unserialize(Checkpoint *cp)
Globals::unserialize(Checkpoint *cp, const std::string &section)
{
const string &section = name();
Tick tick;
paramIn(cp, section, "curTick", tick);
curTick(tick);
@ -510,7 +509,7 @@ Serializable::serializeAll(const string &cpt_dir)
void
Serializable::unserializeGlobals(Checkpoint *cp)
{
globals.unserialize(cp);
globals.unserialize(cp, globals.name());
}
void

2
src/sim/sim_object.cc
View file

@ -169,7 +169,7 @@ SimObject::resume()
}
void
SimObject::setMemoryMode(State new_mode)
SimObject::setMemoryMode(Enums::MemoryMode new_mode)
{
panic("setMemoryMode() should only be called on systems");
}

3
src/sim/sim_object.hh
View file

@ -43,6 +43,7 @@
#include <string>
#include <vector>
#include "enums/MemoryMode.hh"
#include "params/SimObject.hh"
#include "sim/eventq.hh"
#include "sim/serialize.hh"
@ -146,7 +147,7 @@ class SimObject : public EventManager, public Serializable
// before the object will be done draining. Normally this should be 1
virtual unsigned int drain(Event *drain_event);
virtual void resume();
virtual void setMemoryMode(State new_mode);
virtual void setMemoryMode(Enums::MemoryMode new_mode);
virtual void switchOut();
virtual void takeOverFrom(BaseCPU *cpu);

56
src/sim/syscall_emul.hh
View file

@ -400,41 +400,41 @@ convertStatBuf(target_stat &tgt, host_stat *host, bool fakeTTY = false)
tgt->st_dev = 0xA;
else
tgt->st_dev = host->st_dev;
tgt->st_dev = htog(tgt->st_dev);
tgt->st_dev = TheISA::htog(tgt->st_dev);
tgt->st_ino = host->st_ino;
tgt->st_ino = htog(tgt->st_ino);
tgt->st_ino = TheISA::htog(tgt->st_ino);
tgt->st_mode = host->st_mode;
if (fakeTTY) {
// Claim to be a character device
tgt->st_mode &= ~S_IFMT; // Clear S_IFMT
tgt->st_mode |= S_IFCHR; // Set S_IFCHR
}
tgt->st_mode = htog(tgt->st_mode);
tgt->st_mode = TheISA::htog(tgt->st_mode);
tgt->st_nlink = host->st_nlink;
tgt->st_nlink = htog(tgt->st_nlink);
tgt->st_nlink = TheISA::htog(tgt->st_nlink);
tgt->st_uid = host->st_uid;
tgt->st_uid = htog(tgt->st_uid);
tgt->st_uid = TheISA::htog(tgt->st_uid);
tgt->st_gid = host->st_gid;
tgt->st_gid = htog(tgt->st_gid);
tgt->st_gid = TheISA::htog(tgt->st_gid);
if (fakeTTY)
tgt->st_rdev = 0x880d;
else
tgt->st_rdev = host->st_rdev;
tgt->st_rdev = htog(tgt->st_rdev);
tgt->st_rdev = TheISA::htog(tgt->st_rdev);
tgt->st_size = host->st_size;
tgt->st_size = htog(tgt->st_size);
tgt->st_size = TheISA::htog(tgt->st_size);
tgt->st_atimeX = host->st_atime;
tgt->st_atimeX = htog(tgt->st_atimeX);
tgt->st_atimeX = TheISA::htog(tgt->st_atimeX);
tgt->st_mtimeX = host->st_mtime;
tgt->st_mtimeX = htog(tgt->st_mtimeX);
tgt->st_mtimeX = TheISA::htog(tgt->st_mtimeX);
tgt->st_ctimeX = host->st_ctime;
tgt->st_ctimeX = htog(tgt->st_ctimeX);
tgt->st_ctimeX = TheISA::htog(tgt->st_ctimeX);
// Force the block size to be 8k. This helps to ensure buffered io works
// consistently across different hosts.
tgt->st_blksize = 0x2000;
tgt->st_blksize = htog(tgt->st_blksize);
tgt->st_blksize = TheISA::htog(tgt->st_blksize);
tgt->st_blocks = host->st_blocks;
tgt->st_blocks = htog(tgt->st_blocks);
tgt->st_blocks = TheISA::htog(tgt->st_blocks);
}
// Same for stat64
@ -448,11 +448,11 @@ convertStat64Buf(target_stat &tgt, host_stat64 *host, bool fakeTTY = false)
convertStatBuf<target_stat, host_stat64>(tgt, host, fakeTTY);
#if defined(STAT_HAVE_NSEC)
tgt->st_atime_nsec = host->st_atime_nsec;
tgt->st_atime_nsec = htog(tgt->st_atime_nsec);
tgt->st_atime_nsec = TheISA::htog(tgt->st_atime_nsec);
tgt->st_mtime_nsec = host->st_mtime_nsec;
tgt->st_mtime_nsec = htog(tgt->st_mtime_nsec);
tgt->st_mtime_nsec = TheISA::htog(tgt->st_mtime_nsec);
tgt->st_ctime_nsec = host->st_ctime_nsec;
tgt->st_ctime_nsec = htog(tgt->st_ctime_nsec);
tgt->st_ctime_nsec = TheISA::htog(tgt->st_ctime_nsec);
#else
tgt->st_atime_nsec = 0;
tgt->st_mtime_nsec = 0;
@ -966,9 +966,9 @@ writevFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
p->readBlob(tiov_base + i*sizeof(typename OS::tgt_iovec),
(uint8_t*)&tiov, sizeof(typename OS::tgt_iovec));
hiov[i].iov_len = gtoh(tiov.iov_len);
hiov[i].iov_len = TheISA::gtoh(tiov.iov_len);
hiov[i].iov_base = new char [hiov[i].iov_len];
p->readBlob(gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
p->readBlob(TheISA::gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
hiov[i].iov_len);
}
@ -1084,15 +1084,15 @@ getrlimitFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
case OS::TGT_RLIMIT_STACK:
// max stack size in bytes: make up a number (8MB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur);
rlp->rlim_max = htog(rlp->rlim_max);
rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
rlp->rlim_max = TheISA::htog(rlp->rlim_max);
break;
case OS::TGT_RLIMIT_DATA:
// max data segment size in bytes: make up a number
rlp->rlim_cur = rlp->rlim_max = 256 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur);
rlp->rlim_max = htog(rlp->rlim_max);
rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
rlp->rlim_max = TheISA::htog(rlp->rlim_max);
break;
default:
@ -1147,8 +1147,8 @@ utimesFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
struct timeval hostTimeval[2];
for (int i = 0; i < 2; ++i)
{
hostTimeval[i].tv_sec = gtoh((*tp)[i].tv_sec);
hostTimeval[i].tv_usec = gtoh((*tp)[i].tv_usec);
hostTimeval[i].tv_sec = TheISA::gtoh((*tp)[i].tv_sec);
hostTimeval[i].tv_usec = TheISA::gtoh((*tp)[i].tv_usec);
}
// Adjust path for current working directory
@ -1193,8 +1193,8 @@ getrusageFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
switch (who) {
case OS::TGT_RUSAGE_SELF:
getElapsedTime(rup->ru_utime.tv_sec, rup->ru_utime.tv_usec);
rup->ru_utime.tv_sec = htog(rup->ru_utime.tv_sec);
rup->ru_utime.tv_usec = htog(rup->ru_utime.tv_usec);
rup->ru_utime.tv_sec = TheISA::htog(rup->ru_utime.tv_sec);
rup->ru_utime.tv_usec = TheISA::htog(rup->ru_utime.tv_usec);
break;
case OS::TGT_RUSAGE_CHILDREN:
@ -1230,7 +1230,7 @@ timesFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
bufp->tms_cstime = 0;
// Convert to host endianness
bufp->tms_utime = htog(bufp->tms_utime);
bufp->tms_utime = TheISA::htog(bufp->tms_utime);
// Write back
bufp.copyOut(tc->getMemProxy());
@ -1253,7 +1253,7 @@ timeFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
Addr taddr = (Addr)process->getSyscallArg(tc, index);
if(taddr != 0) {
typename OS::time_t t = sec;
t = htog(t);
t = TheISA::htog(t);
SETranslatingPortProxy *p = tc->getMemProxy();
p->writeBlob(taddr, (uint8_t*)&t, (int)sizeof(typename OS::time_t));
}