7d4f187700
This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places.
563 lines
18 KiB
C++
563 lines
18 KiB
C++
/*
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* Copyright (c) 2010-2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#ifndef __CPU_O3_FETCH_HH__
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#define __CPU_O3_FETCH_HH__
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#include "arch/predecoder.hh"
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#include "arch/utility.hh"
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#include "base/statistics.hh"
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#include "config/the_isa.hh"
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#include "cpu/decode.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/timebuf.hh"
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#include "cpu/translation.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "sim/eventq.hh"
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struct DerivO3CPUParams;
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/**
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* DefaultFetch class handles both single threaded and SMT fetch. Its
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* width is specified by the parameters; each cycle it tries to fetch
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* that many instructions. It supports using a branch predictor to
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* predict direction and targets.
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* It supports the idling functionality of the CPU by indicating to
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* the CPU when it is active and inactive.
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*/
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template <class Impl>
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class DefaultFetch
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{
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public:
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/** Typedefs from Impl. */
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::O3CPU O3CPU;
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/** Typedefs from the CPU policy. */
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typedef typename CPUPol::BPredUnit BPredUnit;
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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/** Typedefs from ISA. */
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typedef TheISA::MachInst MachInst;
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typedef TheISA::ExtMachInst ExtMachInst;
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class FetchTranslation : public BaseTLB::Translation
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{
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protected:
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DefaultFetch<Impl> *fetch;
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public:
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FetchTranslation(DefaultFetch<Impl> *_fetch)
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: fetch(_fetch)
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{}
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void
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markDelayed()
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{}
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void
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finish(Fault fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode)
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{
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assert(mode == BaseTLB::Execute);
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fetch->finishTranslation(fault, req);
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delete this;
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}
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};
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private:
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/* Event to delay delivery of a fetch translation result in case of
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* a fault and the nop to carry the fault cannot be generated
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* immediately */
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class FinishTranslationEvent : public Event
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{
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private:
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DefaultFetch<Impl> *fetch;
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Fault fault;
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RequestPtr req;
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public:
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FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
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: fetch(_fetch)
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{}
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void setFault(Fault _fault)
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{
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fault = _fault;
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}
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void setReq(RequestPtr _req)
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{
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req = _req;
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}
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/** Process the delayed finish translation */
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void process()
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{
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assert(fetch->numInst < fetch->fetchWidth);
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fetch->finishTranslation(fault, req);
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}
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const char *description() const
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{
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return "FullO3CPU FetchFinishTranslation";
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}
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};
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public:
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/** Overall fetch status. Used to determine if the CPU can
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* deschedule itsef due to a lack of activity.
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*/
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enum FetchStatus {
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Active,
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Inactive
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};
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/** Individual thread status. */
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enum ThreadStatus {
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Running,
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Idle,
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Squashing,
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Blocked,
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Fetching,
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TrapPending,
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QuiescePending,
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SwitchOut,
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ItlbWait,
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IcacheWaitResponse,
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IcacheWaitRetry,
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IcacheAccessComplete,
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NoGoodAddr
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};
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/** Fetching Policy, Add new policies here.*/
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enum FetchPriority {
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SingleThread,
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RoundRobin,
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Branch,
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IQ,
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LSQ
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};
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private:
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/** Fetch status. */
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FetchStatus _status;
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/** Per-thread status. */
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ThreadStatus fetchStatus[Impl::MaxThreads];
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/** Fetch policy. */
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FetchPriority fetchPolicy;
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/** List that has the threads organized by priority. */
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std::list<ThreadID> priorityList;
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public:
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/** DefaultFetch constructor. */
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DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
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/** Returns the name of fetch. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Sets the main backwards communication time buffer pointer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Sets pointer to time buffer used to communicate to the next stage. */
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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/** Initialize stage. */
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void initStage();
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/** Tells the fetch stage that the Icache is set. */
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void setIcache();
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/** Handles retrying the fetch access. */
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void recvRetry();
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/** Processes cache completion event. */
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void processCacheCompletion(PacketPtr pkt);
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/** Begins the drain of the fetch stage. */
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bool drain();
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/** Resumes execution after a drain. */
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void resume();
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/** Tells fetch stage to prepare to be switched out. */
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void switchOut();
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Checks if the fetch stage is switched out. */
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bool isSwitchedOut() { return switchedOut; }
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/** Tells fetch to wake up from a quiesce instruction. */
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void wakeFromQuiesce();
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private:
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/** Changes the status of this stage to active, and indicates this
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* to the CPU.
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*/
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inline void switchToActive();
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/** Changes the status of this stage to inactive, and indicates
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* this to the CPU.
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*/
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inline void switchToInactive();
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/**
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* Looks up in the branch predictor to see if the next PC should be
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* either next PC+=MachInst or a branch target.
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* @param next_PC Next PC variable passed in by reference. It is
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* expected to be set to the current PC; it will be updated with what
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* the next PC will be.
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* @param next_NPC Used for ISAs which use delay slots.
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* @return Whether or not a branch was predicted as taken.
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*/
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bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
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/**
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* Fetches the cache line that contains fetch_PC. Returns any
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* fault that happened. Puts the data into the class variable
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* cacheData.
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* @param vaddr The memory address that is being fetched from.
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* @param ret_fault The fault reference that will be set to the result of
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* the icache access.
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* @param tid Thread id.
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* @param pc The actual PC of the current instruction.
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* @return Any fault that occured.
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*/
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bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
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void finishTranslation(Fault fault, RequestPtr mem_req);
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/** Check if an interrupt is pending and that we need to handle
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*/
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bool
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checkInterrupt(Addr pc)
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{
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return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
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}
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/** Squashes a specific thread and resets the PC. */
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inline void doSquash(const TheISA::PCState &newPC,
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const DynInstPtr squashInst, ThreadID tid);
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/** Squashes a specific thread and resets the PC. Also tells the CPU to
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* remove any instructions between fetch and decode that should be sqaushed.
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*/
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void squashFromDecode(const TheISA::PCState &newPC,
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const DynInstPtr squashInst,
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const InstSeqNum seq_num, ThreadID tid);
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/** Checks if a thread is stalled. */
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bool checkStall(ThreadID tid) const;
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/** Updates overall fetch stage status; to be called at the end of each
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* cycle. */
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FetchStatus updateFetchStatus();
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public:
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/** Squashes a specific thread and resets the PC. Also tells the CPU to
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* remove any instructions that are not in the ROB. The source of this
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* squash should be the commit stage.
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*/
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void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
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DynInstPtr squashInst, ThreadID tid);
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/** Ticks the fetch stage, processing all inputs signals and fetching
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* as many instructions as possible.
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*/
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void tick();
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/** Checks all input signals and updates the status as necessary.
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* @return: Returns if the status has changed due to input signals.
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*/
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bool checkSignalsAndUpdate(ThreadID tid);
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/** Does the actual fetching of instructions and passing them on to the
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* next stage.
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* @param status_change fetch() sets this variable if there was a status
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* change (ie switching to IcacheMissStall).
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*/
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void fetch(bool &status_change);
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/** Align a PC to the start of an I-cache block. */
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Addr icacheBlockAlignPC(Addr addr)
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{
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return (addr & ~(cacheBlkMask));
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}
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/** The decoder. */
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Decoder decoder;
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private:
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DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
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StaticInstPtr curMacroop, TheISA::PCState thisPC,
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TheISA::PCState nextPC, bool trace);
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/** Returns the appropriate thread to fetch, given the fetch policy. */
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ThreadID getFetchingThread(FetchPriority &fetch_priority);
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/** Returns the appropriate thread to fetch using a round robin policy. */
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ThreadID roundRobin();
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/** Returns the appropriate thread to fetch using the IQ count policy. */
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ThreadID iqCount();
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/** Returns the appropriate thread to fetch using the LSQ count policy. */
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ThreadID lsqCount();
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/** Returns the appropriate thread to fetch using the branch count
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* policy. */
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ThreadID branchCount();
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/** Pipeline the next I-cache access to the current one. */
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void pipelineIcacheAccesses(ThreadID tid);
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/** Profile the reasons of fetch stall. */
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void profileStall(ThreadID tid);
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private:
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/** Pointer to the O3CPU. */
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O3CPU *cpu;
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get decode's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromDecode;
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/** Wire to get rename's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromRename;
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/** Wire to get iew's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's information from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Internal fetch instruction queue. */
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TimeBuffer<FetchStruct> *fetchQueue;
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//Might be annoying how this name is different than the queue.
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/** Wire used to write any information heading to decode. */
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typename TimeBuffer<FetchStruct>::wire toDecode;
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/** BPredUnit. */
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BPredUnit branchPred;
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/** Predecoder. */
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TheISA::Predecoder predecoder;
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TheISA::PCState pc[Impl::MaxThreads];
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Addr fetchOffset[Impl::MaxThreads];
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StaticInstPtr macroop[Impl::MaxThreads];
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/** Can the fetch stage redirect from an interrupt on this instruction? */
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bool delayedCommit[Impl::MaxThreads];
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/** Memory request used to access cache. */
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RequestPtr memReq[Impl::MaxThreads];
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/** Variable that tracks if fetch has written to the time buffer this
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* cycle. Used to tell CPU if there is activity this cycle.
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*/
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bool wroteToTimeBuffer;
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/** Tracks how many instructions has been fetched this cycle. */
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int numInst;
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/** Source of possible stalls. */
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struct Stalls {
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bool decode;
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bool rename;
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bool iew;
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bool commit;
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};
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/** Tracks which stages are telling fetch to stall. */
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Stalls stalls[Impl::MaxThreads];
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/** Decode to fetch delay, in ticks. */
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unsigned decodeToFetchDelay;
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/** Rename to fetch delay, in ticks. */
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unsigned renameToFetchDelay;
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/** IEW to fetch delay, in ticks. */
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unsigned iewToFetchDelay;
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/** Commit to fetch delay, in ticks. */
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unsigned commitToFetchDelay;
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/** The width of fetch in instructions. */
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unsigned fetchWidth;
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/** Is the cache blocked? If so no threads can access it. */
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bool cacheBlocked;
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/** The packet that is waiting to be retried. */
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PacketPtr retryPkt;
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/** The thread that is waiting on the cache to tell fetch to retry. */
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ThreadID retryTid;
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/** Cache block size. */
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int cacheBlkSize;
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/** Mask to get a cache block's address. */
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Addr cacheBlkMask;
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/** The cache line being fetched. */
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uint8_t *cacheData[Impl::MaxThreads];
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/** The PC of the cacheline that has been loaded. */
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Addr cacheDataPC[Impl::MaxThreads];
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/** Whether or not the cache data is valid. */
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bool cacheDataValid[Impl::MaxThreads];
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/** Size of instructions. */
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int instSize;
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/** Icache stall statistics. */
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Counter lastIcacheStall[Impl::MaxThreads];
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/** List of Active Threads */
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std::list<ThreadID> *activeThreads;
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/** Number of threads. */
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ThreadID numThreads;
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/** Number of threads that are actively fetching. */
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ThreadID numFetchingThreads;
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/** Thread ID being fetched. */
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ThreadID threadFetched;
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/** Checks if there is an interrupt pending. If there is, fetch
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* must stop once it is not fetching PAL instructions.
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*/
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bool interruptPending;
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/** Is there a drain pending. */
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bool drainPending;
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/** Records if fetch is switched out. */
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bool switchedOut;
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/** Set to true if a pipelined I-cache request should be issued. */
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bool issuePipelinedIfetch[Impl::MaxThreads];
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/** Event used to delay fault generation of translation faults */
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FinishTranslationEvent finishTranslationEvent;
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// @todo: Consider making these vectors and tracking on a per thread basis.
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/** Stat for total number of cycles stalled due to an icache miss. */
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Stats::Scalar icacheStallCycles;
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/** Stat for total number of fetched instructions. */
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Stats::Scalar fetchedInsts;
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/** Total number of fetched branches. */
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Stats::Scalar fetchedBranches;
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/** Stat for total number of predicted branches. */
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Stats::Scalar predictedBranches;
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/** Stat for total number of cycles spent fetching. */
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Stats::Scalar fetchCycles;
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/** Stat for total number of cycles spent squashing. */
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Stats::Scalar fetchSquashCycles;
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/** Stat for total number of cycles spent waiting for translation */
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Stats::Scalar fetchTlbCycles;
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/** Stat for total number of cycles spent blocked due to other stages in
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* the pipeline.
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*/
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Stats::Scalar fetchIdleCycles;
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/** Total number of cycles spent blocked. */
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Stats::Scalar fetchBlockedCycles;
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/** Total number of cycles spent in any other state. */
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Stats::Scalar fetchMiscStallCycles;
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/** Total number of cycles spent in waiting for drains. */
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Stats::Scalar fetchPendingDrainCycles;
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/** Total number of stall cycles caused by no active threads to run. */
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Stats::Scalar fetchNoActiveThreadStallCycles;
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/** Total number of stall cycles caused by pending traps. */
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Stats::Scalar fetchPendingTrapStallCycles;
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/** Total number of stall cycles caused by pending quiesce instructions. */
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Stats::Scalar fetchPendingQuiesceStallCycles;
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/** Total number of stall cycles caused by I-cache wait retrys. */
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Stats::Scalar fetchIcacheWaitRetryStallCycles;
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/** Stat for total number of fetched cache lines. */
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Stats::Scalar fetchedCacheLines;
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/** Total number of outstanding icache accesses that were dropped
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* due to a squash.
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*/
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Stats::Scalar fetchIcacheSquashes;
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/** Total number of outstanding tlb accesses that were dropped
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* due to a squash.
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*/
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Stats::Scalar fetchTlbSquashes;
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/** Distribution of number of instructions fetched each cycle. */
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Stats::Distribution fetchNisnDist;
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/** Rate of how often fetch was idle. */
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Stats::Formula idleRate;
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/** Number of branch fetches per cycle. */
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Stats::Formula branchRate;
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/** Number of instruction fetched per cycle. */
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Stats::Formula fetchRate;
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};
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#endif //__CPU_O3_FETCH_HH__
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