7d4f187700
This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places.
179 lines
6 KiB
C++
179 lines
6 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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* Jaidev Patwardhan
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* Zhengxing Li
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* Deyuan Guo
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*/
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#include "arch/mips/faults.hh"
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#include "arch/mips/pra_constants.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/MipsPRA.hh"
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#if !FULL_SYSTEM
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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namespace MipsISA
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{
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typedef MipsFaultBase::FaultVals FaultVals;
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template <> FaultVals MipsFault<SystemCallFault>::vals =
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{ "Syscall", 0x180, ExcCodeSys };
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template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
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{ "Reserved Instruction Fault", 0x180, ExcCodeRI };
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template <> FaultVals MipsFault<ThreadFault>::vals =
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{ "Thread Fault", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
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{ "Integer Overflow Exception", 0x180, ExcCodeOv };
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template <> FaultVals MipsFault<TrapFault>::vals =
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{ "Trap", 0x180, ExcCodeTr };
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template <> FaultVals MipsFault<BreakpointFault>::vals =
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{ "Breakpoint", 0x180, ExcCodeBp };
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template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
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{ "DSP Disabled Fault", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<MachineCheckFault>::vals =
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{ "Machine Check", 0x180, ExcCodeMCheck };
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template <> FaultVals MipsFault<ResetFault>::vals =
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{ "Reset Fault", 0x000, ExcCodeDummy };
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template <> FaultVals MipsFault<SoftResetFault>::vals =
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{ "Soft Reset Fault", 0x000, ExcCodeDummy };
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template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
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{ "Non Maskable Interrupt", 0x000, ExcCodeDummy };
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template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
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{ "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
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template <> FaultVals MipsFault<InterruptFault>::vals =
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{ "Interrupt", 0x000, ExcCodeInt };
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template <> FaultVals MipsFault<AddressErrorFault>::vals =
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{ "Address Error", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<TlbInvalidFault>::vals =
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{ "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<TlbRefillFault>::vals =
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{ "TLB Refill Exception", 0x180, ExcCodeDummy };
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template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
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{ "TLB Modified Exception", 0x180, ExcCodeMod };
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void
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MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
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{
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// modify SRS Ctl - Save CSS, put ESS into CSS
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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if (status.exl != 1 && status.bev != 1) {
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// SRS Ctl is modified only if Status_EXL and Status_BEV are not set
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SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
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srsCtl.pss = srsCtl.css;
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srsCtl.css = srsCtl.ess;
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tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
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}
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// set EXL bit (don't care if it is already set!)
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status.exl = 1;
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tc->setMiscRegNoEffect(MISCREG_STATUS, status);
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// write EPC
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PCState pc = tc->pcState();
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DPRINTF(MipsPRA, "PC: %s\n", pc);
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bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
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tc->setMiscRegNoEffect(MISCREG_EPC,
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pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
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// Set Cause_EXCCODE field
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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cause.excCode = excCode;
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cause.bd = delay_slot ? 1 : 0;
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cause.ce = 0;
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tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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}
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void
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MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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if (FULL_SYSTEM) {
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DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
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setExceptionState(tc, code());
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tc->pcState(vect(tc));
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} else {
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panic("Fault %s encountered.\n", name());
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}
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}
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void
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ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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if (FULL_SYSTEM) {
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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/* All reset activity must be invoked from here */
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Addr handler = vect(tc);
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tc->pcState(handler);
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DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
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}
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// Set Coprocessor 1 (Floating Point) To Usable
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StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
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status.cu.cu1 = 1;
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tc->setMiscReg(MISCREG_STATUS, status);
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}
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void
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SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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panic("Soft reset not implemented.\n");
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}
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void
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NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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panic("Non maskable interrupt not implemented.\n");
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}
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} // namespace MipsISA
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