7d4f187700
This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places.
544 lines
17 KiB
C++
544 lines
17 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Steve Reinhardt
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* Ron Dreslinski
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*/
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/**
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* @file
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* Declares a basic cache interface BaseCache.
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*/
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#ifndef __BASE_CACHE_HH__
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#define __BASE_CACHE_HH__
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#include <algorithm>
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#include <list>
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#include <string>
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#include <vector>
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "debug/Cache.hh"
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#include "debug/CachePort.hh"
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#include "mem/cache/mshr_queue.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "mem/tport.hh"
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#include "params/BaseCache.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_exit.hh"
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class MSHR;
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/**
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* A basic cache interface. Implements some common functions for speed.
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*/
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class BaseCache : public MemObject
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{
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/**
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* Indexes to enumerate the MSHR queues.
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*/
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enum MSHRQueueIndex {
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MSHRQueue_MSHRs,
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MSHRQueue_WriteBuffer
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};
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public:
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/**
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* Reasons for caches to be blocked.
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*/
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enum BlockedCause {
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Blocked_NoMSHRs = MSHRQueue_MSHRs,
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Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
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Blocked_NoTargets,
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NUM_BLOCKED_CAUSES
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};
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/**
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* Reasons for cache to request a bus.
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*/
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enum RequestCause {
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Request_MSHR = MSHRQueue_MSHRs,
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Request_WB = MSHRQueue_WriteBuffer,
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Request_PF,
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NUM_REQUEST_CAUSES
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};
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protected:
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class CachePort : public SimpleTimingPort
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{
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public:
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BaseCache *cache;
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protected:
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CachePort(const std::string &_name, BaseCache *_cache,
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const std::string &_label);
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virtual unsigned deviceBlockSize() const;
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bool recvRetryCommon();
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typedef EventWrapper<Port, &Port::sendRetry>
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SendRetryEvent;
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const std::string label;
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public:
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void setBlocked();
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void clearBlocked();
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bool checkFunctional(PacketPtr pkt);
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bool blocked;
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bool mustSendRetry;
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void requestBus(RequestCause cause, Tick time)
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{
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DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
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if (!waitingOnRetry) {
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schedSendEvent(time);
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}
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}
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void respond(PacketPtr pkt, Tick time) {
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schedSendTiming(pkt, time);
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}
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};
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CachePort *cpuSidePort;
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CachePort *memSidePort;
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protected:
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/** Miss status registers */
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MSHRQueue mshrQueue;
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/** Write/writeback buffer */
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MSHRQueue writeBuffer;
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MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
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PacketPtr pkt, Tick time, bool requestBus)
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{
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MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
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if (mq->isFull()) {
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setBlocked((BlockedCause)mq->index);
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}
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if (requestBus) {
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requestMemSideBus((RequestCause)mq->index, time);
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}
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return mshr;
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}
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void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
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{
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MSHRQueue *mq = mshr->queue;
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bool wasFull = mq->isFull();
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mq->markInService(mshr, pkt);
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if (wasFull && !mq->isFull()) {
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clearBlocked((BlockedCause)mq->index);
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}
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}
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/** Block size of this cache */
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const unsigned blkSize;
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/**
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* The latency of a hit in this device.
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*/
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int hitLatency;
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/** The number of targets for each MSHR. */
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const int numTarget;
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/** Do we forward snoops from mem side port through to cpu side port? */
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bool forwardSnoops;
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/** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
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* never try to forward ownership and similar optimizations to the cpu
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* side */
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bool isTopLevel;
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/**
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* Bit vector of the blocking reasons for the access path.
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* @sa #BlockedCause
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*/
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uint8_t blocked;
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/** Increasing order number assigned to each incoming request. */
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uint64_t order;
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/** Stores time the cache blocked for statistics. */
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Tick blockedCycle;
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/** Pointer to the MSHR that has no targets. */
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MSHR *noTargetMSHR;
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/** The number of misses to trigger an exit event. */
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Counter missCount;
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/** The drain event. */
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Event *drainEvent;
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/**
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* The address range to which the cache responds on the CPU side.
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* Normally this is all possible memory addresses. */
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Range<Addr> addrRange;
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/** number of cpus sharing this cache - from config file */
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int _numCpus;
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public:
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int numCpus() { return _numCpus; }
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// Statistics
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/**
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* @addtogroup CacheStatistics
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* @{
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*/
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/** Number of hits per thread for each type of command. @sa Packet::Command */
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Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
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/** Number of hits for demand accesses. */
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Stats::Formula demandHits;
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/** Number of hit for all accesses. */
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Stats::Formula overallHits;
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/** Number of misses per thread for each type of command. @sa Packet::Command */
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Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
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/** Number of misses for demand accesses. */
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Stats::Formula demandMisses;
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/** Number of misses for all accesses. */
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Stats::Formula overallMisses;
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/**
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* Total number of cycles per thread/command spent waiting for a miss.
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* Used to calculate the average miss latency.
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*/
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Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
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/** Total number of cycles spent waiting for demand misses. */
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Stats::Formula demandMissLatency;
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/** Total number of cycles spent waiting for all misses. */
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Stats::Formula overallMissLatency;
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/** The number of accesses per command and thread. */
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Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
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/** The number of demand accesses. */
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Stats::Formula demandAccesses;
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/** The number of overall accesses. */
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Stats::Formula overallAccesses;
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/** The miss rate per command and thread. */
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Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
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/** The miss rate of all demand accesses. */
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Stats::Formula demandMissRate;
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/** The miss rate for all accesses. */
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Stats::Formula overallMissRate;
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/** The average miss latency per command and thread. */
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Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
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/** The average miss latency for demand misses. */
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Stats::Formula demandAvgMissLatency;
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/** The average miss latency for all misses. */
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Stats::Formula overallAvgMissLatency;
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/** The total number of cycles blocked for each blocked cause. */
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Stats::Vector blocked_cycles;
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/** The number of times this cache blocked for each blocked cause. */
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Stats::Vector blocked_causes;
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/** The average number of cycles blocked for each blocked cause. */
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Stats::Formula avg_blocked;
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/** The number of fast writes (WH64) performed. */
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Stats::Scalar fastWrites;
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/** The number of cache copies performed. */
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Stats::Scalar cacheCopies;
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/** Number of blocks written back per thread. */
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Stats::Vector writebacks;
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/** Number of misses that hit in the MSHRs per command and thread. */
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Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
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/** Demand misses that hit in the MSHRs. */
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Stats::Formula demandMshrHits;
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/** Total number of misses that hit in the MSHRs. */
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Stats::Formula overallMshrHits;
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/** Number of misses that miss in the MSHRs, per command and thread. */
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Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
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/** Demand misses that miss in the MSHRs. */
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Stats::Formula demandMshrMisses;
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/** Total number of misses that miss in the MSHRs. */
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Stats::Formula overallMshrMisses;
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/** Number of misses that miss in the MSHRs, per command and thread. */
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Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
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/** Total number of misses that miss in the MSHRs. */
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Stats::Formula overallMshrUncacheable;
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/** Total cycle latency of each MSHR miss, per command and thread. */
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Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
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/** Total cycle latency of demand MSHR misses. */
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Stats::Formula demandMshrMissLatency;
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/** Total cycle latency of overall MSHR misses. */
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Stats::Formula overallMshrMissLatency;
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/** Total cycle latency of each MSHR miss, per command and thread. */
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Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
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/** Total cycle latency of overall MSHR misses. */
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Stats::Formula overallMshrUncacheableLatency;
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#if 0
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/** The total number of MSHR accesses per command and thread. */
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Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
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/** The total number of demand MSHR accesses. */
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Stats::Formula demandMshrAccesses;
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/** The total number of MSHR accesses. */
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Stats::Formula overallMshrAccesses;
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#endif
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/** The miss rate in the MSHRs pre command and thread. */
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Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
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/** The demand miss rate in the MSHRs. */
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Stats::Formula demandMshrMissRate;
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/** The overall miss rate in the MSHRs. */
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Stats::Formula overallMshrMissRate;
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/** The average latency of an MSHR miss, per command and thread. */
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Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
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/** The average latency of a demand MSHR miss. */
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Stats::Formula demandAvgMshrMissLatency;
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/** The average overall latency of an MSHR miss. */
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Stats::Formula overallAvgMshrMissLatency;
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/** The average latency of an MSHR miss, per command and thread. */
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Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
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/** The average overall latency of an MSHR miss. */
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Stats::Formula overallAvgMshrUncacheableLatency;
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/** The number of times a thread hit its MSHR cap. */
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Stats::Vector mshr_cap_events;
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/** The number of times software prefetches caused the MSHR to block. */
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Stats::Vector soft_prefetch_mshr_full;
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Stats::Scalar mshr_no_allocate_misses;
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/**
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* @}
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*/
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/**
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* Register stats for this object.
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*/
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virtual void regStats();
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public:
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typedef BaseCacheParams Params;
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BaseCache(const Params *p);
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~BaseCache() {}
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virtual void init();
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/**
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* Query block size of a cache.
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* @return The block size
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*/
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unsigned
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getBlockSize() const
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{
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return blkSize;
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}
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Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
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const Range<Addr> &getAddrRange() const { return addrRange; }
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MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
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{
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assert(!pkt->req->isUncacheable());
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return allocateBufferInternal(&mshrQueue,
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blockAlign(pkt->getAddr()), blkSize,
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pkt, time, requestBus);
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}
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MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
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{
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assert(pkt->isWrite() && !pkt->isRead());
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return allocateBufferInternal(&writeBuffer,
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pkt->getAddr(), pkt->getSize(),
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pkt, time, requestBus);
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}
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MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
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{
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assert(pkt->req->isUncacheable());
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assert(pkt->isRead());
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return allocateBufferInternal(&mshrQueue,
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pkt->getAddr(), pkt->getSize(),
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pkt, time, requestBus);
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}
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/**
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* Returns true if the cache is blocked for accesses.
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*/
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bool isBlocked()
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{
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return blocked != 0;
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}
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/**
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* Marks the access path of the cache as blocked for the given cause. This
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* also sets the blocked flag in the slave interface.
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* @param cause The reason for the cache blocking.
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*/
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void setBlocked(BlockedCause cause)
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{
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uint8_t flag = 1 << cause;
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if (blocked == 0) {
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blocked_causes[cause]++;
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blockedCycle = curTick();
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cpuSidePort->setBlocked();
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}
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blocked |= flag;
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DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
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}
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/**
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* Marks the cache as unblocked for the given cause. This also clears the
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* blocked flags in the appropriate interfaces.
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* @param cause The newly unblocked cause.
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* @warning Calling this function can cause a blocked request on the bus to
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* access the cache. The cache must be in a state to handle that request.
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*/
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void clearBlocked(BlockedCause cause)
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{
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uint8_t flag = 1 << cause;
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blocked &= ~flag;
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DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
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if (blocked == 0) {
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blocked_cycles[cause] += curTick() - blockedCycle;
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cpuSidePort->clearBlocked();
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}
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}
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/**
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* Request the master bus for the given cause and time.
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* @param cause The reason for the request.
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* @param time The time to make the request.
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*/
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void requestMemSideBus(RequestCause cause, Tick time)
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{
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memSidePort->requestBus(cause, time);
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}
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/**
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* Clear the master bus request for the given cause.
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* @param cause The request reason to clear.
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*/
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void deassertMemSideBusRequest(RequestCause cause)
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{
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// Obsolete... we no longer signal bus requests explicitly so
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// we can't deassert them. Leaving this in as a no-op since
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// the prefetcher calls it to indicate that it no longer wants
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// to request a prefetch, and someday that might be
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// interesting again.
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}
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virtual unsigned int drain(Event *de);
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virtual bool inCache(Addr addr) = 0;
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virtual bool inMissQueue(Addr addr) = 0;
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void incMissCount(PacketPtr pkt, int id)
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{
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if (pkt->cmd == MemCmd::Writeback) {
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assert(id == -1);
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misses[pkt->cmdToIndex()][0]++;
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/* same thing for writeback hits as misses - no context id
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* available, meanwhile writeback hit/miss stats are not used
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* in any aggregate hit/miss calculations, so just lump them all
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* in bucket 0 */
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#if FULL_SYSTEM
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} else if (id == -1) {
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// Device accesses have id -1
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// lump device accesses into their own bucket
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misses[pkt->cmdToIndex()][_numCpus]++;
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#endif
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} else {
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misses[pkt->cmdToIndex()][id % _numCpus]++;
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}
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if (missCount) {
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--missCount;
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if (missCount == 0)
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exitSimLoop("A cache reached the maximum miss count");
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}
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}
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void incHitCount(PacketPtr pkt, int id)
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{
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/* Writeback requests don't have a context id associated with
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* them, so attributing a hit to a -1 context id is obviously a
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* problem. I've noticed in the stats that hits are split into
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* demand and non-demand hits - neither of which include writeback
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* hits, so here, I'll just put the writeback hits into bucket 0
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* since it won't mess with any other stats -hsul */
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if (pkt->cmd == MemCmd::Writeback) {
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assert(id == -1);
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hits[pkt->cmdToIndex()][0]++;
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#if FULL_SYSTEM
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} else if (id == -1) {
|
|
// Device accesses have id -1
|
|
// lump device accesses into their own bucket
|
|
hits[pkt->cmdToIndex()][_numCpus]++;
|
|
#endif
|
|
} else {
|
|
/* the % is necessary in case there are switch cpus */
|
|
hits[pkt->cmdToIndex()][id % _numCpus]++;
|
|
}
|
|
}
|
|
|
|
};
|
|
|
|
#endif //__BASE_CACHE_HH__
|