x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for cpus that will be switched in later
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e11847bfa9
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c80af04d7d
4 changed files with 28 additions and 8 deletions
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@ -70,6 +70,7 @@ def config_cache(options, system):
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PageTableWalkerCache())
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else:
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
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system.cpu[i].createInterruptController()
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if options.l2cache:
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system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
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else:
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@ -188,6 +188,7 @@ if len(bm) == 2:
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drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.createInterruptController()
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drive_sys.cpu.connectAllPorts(drive_sys.membus)
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if options.fastmem:
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drive_sys.cpu.physmem_port = drive_sys.physmem.port
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@ -100,33 +100,32 @@ class BaseCPU(MemObject):
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dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
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itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
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interrupts = Param.SparcInterrupts(
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SparcInterrupts(), "Interrupt Controller")
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NULL, "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'alpha':
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dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
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interrupts = Param.AlphaInterrupts(
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AlphaInterrupts(), "Interrupt Controller")
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NULL, "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'x86':
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dtb = Param.X86TLB(X86TLB(), "Data TLB")
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itb = Param.X86TLB(X86TLB(), "Instruction TLB")
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_localApic = X86LocalApic(pio_addr=0x2000000000000000)
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interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
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interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'mips':
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dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
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itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
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interrupts = Param.MipsInterrupts(
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MipsInterrupts(), "Interrupt Controller")
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NULL, "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'arm':
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dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
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itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
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interrupts = Param.ArmInterrupts(
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ArmInterrupts(), "Interrupt Controller")
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NULL, "Interrupt Controller")
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elif buildEnv['TARGET_ISA'] == 'power':
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UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
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dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
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itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
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interrupts = Param.PowerInterrupts(
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PowerInterrupts(), "Interrupt Controller")
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NULL, "Interrupt Controller")
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else:
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print "Don't know what TLB to use for ISA %s" % \
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buildEnv['TARGET_ISA']
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@ -164,6 +163,25 @@ class BaseCPU(MemObject):
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_uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
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_uncached_master_ports += ["interrupts.int_master"]
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def createInterruptController(self):
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if buildEnv['TARGET_ISA'] == 'sparc':
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self.interrupts = SparcInterrupts()
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elif buildEnv['TARGET_ISA'] == 'alpha':
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self.interrupts = AlphaInterrupts()
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elif buildEnv['TARGET_ISA'] == 'x86':
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_localApic = X86LocalApic(pio_addr=0x2000000000000000)
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self.interrupts = _localApic
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elif buildEnv['TARGET_ISA'] == 'mips':
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self.interrupts = MipsInterrupts()
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elif buildEnv['TARGET_ISA'] == 'arm':
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self.interrupts = ArmInterrupts()
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elif buildEnv['TARGET_ISA'] == 'power':
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self.interrupts = PowerInterrupts()
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else:
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print "Don't know what Interrupt Controller to use for ISA %s" % \
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buildEnv['TARGET_ISA']
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sys.exit(1)
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def connectCachedPorts(self, bus):
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for p in self._cached_ports:
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exec('self.%s = bus.slave' % p)
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@ -653,7 +653,7 @@ FullO3CPU<Impl>::init()
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if (icachePort.isConnected())
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fetch.setIcache();
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if (FullSystem) {
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if (FullSystem && !params()->defer_registration) {
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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ThreadContext *src_tc = threadContexts[tid];
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TheISA::initCPU(src_tc, src_tc->contextId());
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