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SE/FS: Build the devices in SE mode.

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This commit is contained in:
Gabe Black 2011-09-30 00:28:33 -07:00
parent 35e20c7470
commit 51f7a66660
25 changed files with 129 additions and 92 deletions
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4
src/arch/sparc/isa_traits.hh
View file

@ -35,7 +35,6 @@
#include "arch/sparc/sparc_traits.hh"
#include "arch/sparc/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace BigEndianGuest {}
@ -78,7 +77,6 @@ const Addr VAddrAMask = ULL(0xFFFFFFFF);
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
#if FULL_SYSTEM
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,
@ -91,8 +89,6 @@ enum InterruptTypes
NumInterruptTypes
};
#endif
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
}

8
src/base/vnc/SConscript
View file

@ -39,10 +39,8 @@
Import('*')
if env['FULL_SYSTEM']:
SimObject('VncServer.py')
Source('vncserver.cc')
DebugFlag('VNC')
Source('convert.cc')
SimObject('VncServer.py')
Source('vncserver.cc')
DebugFlag('VNC')

5
src/cpu/SConscript
View file

@ -109,6 +109,7 @@ SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
SimObject('IntrControl.py')
SimObject('NativeTrace.py')
Source('activity.cc')
@ -118,6 +119,7 @@ Source('decode.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
Source('intr_control.cc')
Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
@ -127,9 +129,6 @@ Source('thread_context.cc')
Source('thread_state.cc')
if env['FULL_SYSTEM']:
SimObject('IntrControl.py')
Source('intr_control.cc')
Source('profile.cc')
if env['TARGET_ISA'] == 'sparc':

8
src/cpu/intr_control.cc
View file

@ -48,19 +48,27 @@ IntrControl::IntrControl(const Params *p)
void
IntrControl::post(int cpu_id, int int_num, int index)
{
#if FULL_SYSTEM
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->postInterrupt(int_num, index);
#else
panic("Called IntrControl::post in SE mode.\n");
#endif
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
#if FULL_SYSTEM
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->clearInterrupt(int_num, index);
#else
panic("Called IntrControl::clear in SE mode.\n");
#endif
}
IntrControl *

144
src/dev/SConscript
View file

@ -34,79 +34,77 @@ Import('*')
if env['TARGET_ISA'] == 'no':
Return()
if env['FULL_SYSTEM']:
SimObject('BadDevice.py')
SimObject('CopyEngine.py')
SimObject('Device.py')
SimObject('DiskImage.py')
SimObject('Ethernet.py')
SimObject('Ide.py')
SimObject('Pci.py')
SimObject('Platform.py')
SimObject('SimpleDisk.py')
SimObject('Terminal.py')
SimObject('Uart.py')
SimObject('BadDevice.py')
SimObject('CopyEngine.py')
SimObject('Device.py')
SimObject('DiskImage.py')
SimObject('Ethernet.py')
SimObject('Ide.py')
SimObject('Pci.py')
SimObject('Platform.py')
SimObject('SimpleDisk.py')
SimObject('Terminal.py')
SimObject('Uart.py')
Source('baddev.cc')
Source('copy_engine.cc')
Source('disk_image.cc')
Source('etherbus.cc')
Source('etherdevice.cc')
Source('etherdump.cc')
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
Source('ethertap.cc')
Source('i8254xGBe.cc')
Source('ide_ctrl.cc')
Source('ide_disk.cc')
Source('intel_8254_timer.cc')
Source('io_device.cc')
Source('isa_fake.cc')
Source('mc146818.cc')
Source('ns_gige.cc')
Source('pciconfigall.cc')
Source('pcidev.cc')
Source('pktfifo.cc')
Source('platform.cc')
Source('ps2.cc')
Source('simple_disk.cc')
Source('sinic.cc')
Source('terminal.cc')
Source('uart.cc')
Source('uart8250.cc')
Source('baddev.cc')
Source('copy_engine.cc')
Source('disk_image.cc')
Source('etherbus.cc')
Source('etherdevice.cc')
Source('etherdump.cc')
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
Source('ethertap.cc')
Source('i8254xGBe.cc')
Source('ide_ctrl.cc')
Source('ide_disk.cc')
Source('intel_8254_timer.cc')
Source('io_device.cc')
Source('isa_fake.cc')
Source('mc146818.cc')
Source('ns_gige.cc')
Source('pciconfigall.cc')
Source('pcidev.cc')
Source('pktfifo.cc')
Source('platform.cc')
Source('ps2.cc')
Source('simple_disk.cc')
Source('sinic.cc')
Source('terminal.cc')
Source('uart.cc')
Source('uart8250.cc')
DebugFlag('DiskImageRead')
DebugFlag('DiskImageWrite')
DebugFlag('DMA')
DebugFlag('DMACopyEngine')
DebugFlag('Ethernet')
DebugFlag('EthernetCksum')
DebugFlag('EthernetDMA')
DebugFlag('EthernetData')
DebugFlag('EthernetDesc')
DebugFlag('EthernetEEPROM')
DebugFlag('EthernetIntr')
DebugFlag('EthernetPIO')
DebugFlag('EthernetSM')
DebugFlag('IdeCtrl')
DebugFlag('IdeDisk')
DebugFlag('Intel8254Timer')
DebugFlag('IsaFake')
DebugFlag('MC146818')
DebugFlag('PCIDEV')
DebugFlag('PciConfigAll')
DebugFlag('SimpleDisk')
DebugFlag('SimpleDiskData')
DebugFlag('Terminal')
DebugFlag('TerminalVerbose')
DebugFlag('Uart')
CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
'EthernetCksum', 'EthernetEEPROM' ])
CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
DebugFlag('DiskImageRead')
DebugFlag('DiskImageWrite')
DebugFlag('DMA')
DebugFlag('DMACopyEngine')
DebugFlag('Ethernet')
DebugFlag('EthernetCksum')
DebugFlag('EthernetDMA')
DebugFlag('EthernetData')
DebugFlag('EthernetDesc')
DebugFlag('EthernetEEPROM')
DebugFlag('EthernetIntr')
DebugFlag('EthernetPIO')
DebugFlag('EthernetSM')
DebugFlag('IdeCtrl')
DebugFlag('IdeDisk')
DebugFlag('Intel8254Timer')
DebugFlag('IsaFake')
DebugFlag('MC146818')
DebugFlag('PCIDEV')
DebugFlag('PciConfigAll')
DebugFlag('SimpleDisk')
DebugFlag('SimpleDiskData')
DebugFlag('Terminal')
DebugFlag('TerminalVerbose')
DebugFlag('Uart')
CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
'EthernetCksum', 'EthernetEEPROM' ])
CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])

4
src/dev/alpha/AlphaBackdoor.py
View file

@ -26,6 +26,7 @@
#
# Authors: Nathan Binkert
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
@ -35,4 +36,5 @@ class AlphaBackdoor(BasicPioDevice):
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
terminal = Param.Terminal(Parent.any, "The console terminal")
system = Param.AlphaSystem(Parent.any, "system object")
if buildEnv['FULL_SYSTEM']: # No AlphaSystem in SE mode.
system = Param.AlphaSystem(Parent.any, "system object")

2
src/dev/alpha/SConscript
View file

@ -31,7 +31,7 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
if env['TARGET_ISA'] == 'alpha':
SimObject('AlphaBackdoor.py')
SimObject('Tsunami.py')

11
src/dev/alpha/backdoor.cc
View file

@ -38,7 +38,11 @@
#include <cstddef>
#include <string>
#include "config/full_system.hh"
#if FULL_SYSTEM //XXX No AlphaSystem in SE mode.
#include "arch/alpha/system.hh"
#endif
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
@ -60,7 +64,10 @@ using namespace AlphaISA;
AlphaBackdoor::AlphaBackdoor(const Params *p)
: BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
system(p->system), cpu(p->cpu)
#if FULL_SYSTEM //XXX No system pointer in SE mode.
system(p->system),
#endif
cpu(p->cpu)
{
pioSize = sizeof(struct AlphaAccess);
@ -84,6 +91,7 @@ AlphaBackdoor::AlphaBackdoor(const Params *p)
void
AlphaBackdoor::startup()
{
#if FULL_SYSTEM //XXX No system pointer in SE mode.
system->setAlphaAccess(pioAddr);
alphaAccess->numCPUs = system->numContexts();
alphaAccess->kernStart = system->getKernelStart();
@ -92,6 +100,7 @@ AlphaBackdoor::startup()
alphaAccess->mem_size = system->physmem->size();
alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
#endif
}
Tick

2
src/dev/alpha/backdoor.hh
View file

@ -92,8 +92,10 @@ class AlphaBackdoor : public BasicPioDevice
/** the system console (the terminal) is accessable from the console */
Terminal *terminal;
#if FULL_SYSTEM //XXX No AlphaSystem defined in SE mode.
/** a pointer to the system we are running in */
AlphaSystem *system;
#endif
/** a pointer to the CPU boot cpu */
BaseCPU *cpu;

2
src/dev/alpha/tsunami.cc
View file

@ -52,8 +52,10 @@ using namespace TheISA;
Tsunami::Tsunami(const Params *p)
: Platform(p), system(p->system)
{
#if FULL_SYSTEM //XXX No platform pointer in SE mode.
// set the back pointer from the system to myself
system->platform = this;
#endif
for (int i = 0; i < Tsunami::Max_CPUs; i++)
intr_sum_type[i] = 0;

2
src/dev/arm/SConscript
View file

@ -39,7 +39,7 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
if env['TARGET_ISA'] == 'arm':
SimObject('RealView.py')
Source('a9scu.cc')

1
src/dev/arm/gic.cc
View file

@ -45,6 +45,7 @@
#include "debug/Checkpoint.hh"
#include "debug/GIC.hh"
#include "debug/IPI.hh"
#include "debug/Interrupt.hh"
#include "dev/arm/gic.hh"
#include "dev/arm/realview.hh"
#include "dev/terminal.hh"

2
src/dev/arm/realview.cc
View file

@ -61,8 +61,10 @@ using namespace TheISA;
RealView::RealView(const Params *p)
: Platform(p), system(p->system)
{
#if FULL_SYSTEM //XXX No platform pointer on the system object in SE mode.
// set the back pointer from the system to myself
system->platform = this;
#endif
}
Tick

2
src/dev/mips/SConscript
View file

@ -31,7 +31,7 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
if env['TARGET_ISA'] == 'mips':
SimObject('Malta.py')
DebugFlag('Malta')

3
src/dev/mips/malta.cc
View file

@ -39,6 +39,7 @@
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"
@ -53,8 +54,10 @@ using namespace TheISA;
Malta::Malta(const Params *p)
: Platform(p), system(p->system)
{
#if FULL_SYSTEM //XXX No platform pointer on the system object in SE mode.
// set the back pointer from the system to myself
system->platform = this;
#endif
for (int i = 0; i < Malta::Max_CPUs; i++)
intr_sum_type[i] = 0;

1
src/dev/mips/malta_cchip.cc
View file

@ -42,6 +42,7 @@
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/maltareg.h"

1
src/dev/mips/malta_io.cc
View file

@ -43,6 +43,7 @@
#include "base/time.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"

1
src/dev/mips/malta_pchip.cc
View file

@ -39,6 +39,7 @@
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_pchip.hh"
#include "dev/mips/maltareg.h"

2
src/dev/simple_disk.cc
View file

@ -70,7 +70,9 @@ SimpleDisk::read(Addr addr, baddr_t block, int count) const
for (int i = 0, j = 0; i < count; i += SectorSize, j++)
image->read(data + i, block + j);
#if FULL_SYSTEM //XXX No functional port in SE mode.
system->functionalPort->writeBlob(addr, data, count);
#endif
DPRINTF(SimpleDisk, "read block=%#x len=%d\n", (uint64_t)block, count);
DDUMP(SimpleDiskData, data, count);

2
src/dev/sparc/SConscript
View file

@ -31,7 +31,7 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
if env['TARGET_ISA'] == 'sparc':
SimObject('T1000.py')
Source('dtod.cc')

1
src/dev/sparc/iob.cc
View file

@ -42,6 +42,7 @@
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "debug/Iob.hh"
#include "dev/sparc/iob.hh"
#include "dev/platform.hh"

2
src/dev/sparc/t1000.cc
View file

@ -49,8 +49,10 @@ using namespace TheISA;
T1000::T1000(const Params *p)
: Platform(p), system(p->system)
{
#if FULL_SYSTEM //XXX No platform pointer on system objects in SE mode.
// set the back pointer from the system to myself
system->platform = this;
#endif
}
Tick

2
src/dev/x86/SConscript
View file

@ -30,7 +30,7 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
if env['TARGET_ISA'] == 'x86':
SimObject('Pc.py')
Source('pc.cc')

7
src/dev/x86/i82094aa.cc
View file

@ -28,7 +28,12 @@
* Authors: Gabe Black
*/
#include "config/full_system.hh"
#if FULL_SYSTEM
#include "arch/x86/interrupts.hh"
#endif
#include "arch/x86/intmessage.hh"
#include "debug/I82094AA.hh"
#include "dev/x86/i82094aa.hh"
@ -167,6 +172,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
DPRINTF(I82094AA, "Entry was masked.\n");
return;
} else {
#if FULL_SYSTEM //XXX No interrupt controller in SE mode.
TriggerIntMessage message = 0;
message.destination = entry.dest;
if (entry.deliveryMode == DeliveryMode::ExtInt) {
@ -225,6 +231,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
}
intPort->sendMessage(apics, message,
sys->getMemoryMode() == Enums::timing);
#endif
}
}

2
src/dev/x86/pc.cc
View file

@ -56,7 +56,9 @@ Pc::Pc(const Params *p)
{
southBridge = NULL;
// set the back pointer from the system to myself
#if FULL_SYSTEM //XXX No platform pointer in SE mode.
system->platform = this;
#endif
}
void