SE/FS: Use the new FullSystem constant where possible.
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4fcf8e9959
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35e20c7470
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@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
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0x6c: decode RA {
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31: decode IMM {
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1: decode INTIMM {
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// return EV5 for FULL_SYSTEM and EV6 otherwise
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1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
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// return EV5 for FullSystem and EV6 otherwise
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1: implver({{ Rc = FullSystem ? 1 : 2 }});
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}
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}
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}
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@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
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* the parser to understand that.
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*/
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uint64_t unused_var M5_VAR_USED = Rb;
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Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
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Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
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}}, IsUnverifiable);
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// All of the barrier instructions below do nothing in
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@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
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0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
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}
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0xe000: decode FULL_SYSTEM {
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0xe000: decode FullSystem {
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0: FailUnimpl::rc_se();
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default: BasicOperate::rc({{
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Ra = IntrFlag;
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IntrFlag = 0;
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}}, IsNonSpeculative, IsUnverifiable);
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}
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0xf000: decode FULL_SYSTEM {
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0xf000: decode FullSystem {
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0: FailUnimpl::rs_se();
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default: BasicOperate::rs({{
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Ra = IntrFlag;
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@ -45,7 +45,7 @@ output exec {{
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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Fault fault = NoFault; // dummy... this ipr access should not fault
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if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
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if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
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fault = new FloatEnableFault;
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}
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return fault;
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@ -64,6 +64,7 @@ output decoder {{
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#include "config/ss_compatible_fp.hh"
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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#include "mem/packet.hh"
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#include "sim/full_system.hh"
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using namespace AlphaISA;
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}};
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@ -81,6 +82,7 @@ output exec {{
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#include "cpu/exetrace.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/full_system.hh"
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#include "sim/pseudo_inst.hh"
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#include "sim/sim_exit.hh"
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@ -42,6 +42,7 @@
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/TLB.hh"
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#include "sim/full_system.hh"
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using namespace std;
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@ -370,7 +371,7 @@ Fault
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TLB::translateInst(RequestPtr req, ThreadContext *tc)
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{
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//If this is a pal pc, then set PHYSICAL
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if (FULL_SYSTEM && PcPAL(req->getPC()))
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if (FullSystem && PcPAL(req->getPC()))
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req->setFlags(Request::PHYSICAL);
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if (PcPAL(req->getPC())) {
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@ -134,7 +134,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
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void
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MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
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setExceptionState(tc, code());
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tc->pcState(vect(tc));
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@ -146,7 +146,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
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void
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ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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/* All reset activity must be invoked from here */
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Addr handler = vect(tc);
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@ -38,6 +38,7 @@
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#include "cpu/thread_context.hh"
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#include "debug/MipsPRA.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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namespace MipsISA
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{
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@ -163,7 +164,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
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StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{
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MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
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if (FULL_SYSTEM) {
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if (FullSystem) {
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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cause.ce = coProcID;
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tc->setMiscReg(MISCREG_CAUSE, cause);
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@ -197,7 +198,7 @@ class AddressFault : public MipsFault<T>
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StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{
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MipsFault<T>::invoke(tc, inst);
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if (FULL_SYSTEM)
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if (FullSystem)
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
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}
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};
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@ -249,7 +250,7 @@ class TlbFault : public AddressFault<T>
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invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
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tc->pcState(this->vect(tc));
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setTlbExceptionState(tc, this->code());
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@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
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format BasicOp {
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0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
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0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
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0x4: decode FULL_SYSTEM {
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0x4: decode FullSystem {
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0: syscall_se({{ xc->syscall(R2); }},
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IsSerializeAfter, IsNonSpeculative);
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default: syscall({{ fault = new SystemCallFault(); }});
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@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: add({{
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IntReg result;
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Rd = result = Rs + Rt;
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if (FULL_SYSTEM &&
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if (FullSystem &&
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findOverflow(32, result, Rs, Rt)) {
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fault = new IntegerOverflowFault();
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}
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@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x2: sub({{
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IntReg result;
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Rd = result = Rs - Rt;
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if (FULL_SYSTEM &&
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if (FullSystem &&
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findOverflow(32, result, Rs, ~Rt)) {
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fault = new IntegerOverflowFault();
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}
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@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: addi({{
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IntReg result;
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Rt = result = Rs + imm;
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if (FULL_SYSTEM &&
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if (FullSystem &&
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findOverflow(32, result, Rs, imm)) {
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fault = new IntegerOverflowFault();
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}
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@ -2433,7 +2433,7 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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}
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0x3: decode OP default FailUnimpl::rdhwr() {
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0x0: decode FULL_SYSTEM {
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0x0: decode FullSystem {
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0: decode RD {
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29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
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}
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@ -128,7 +128,7 @@ def template ControlTLBExecute {{
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%(op_decl)s;
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%(op_rd)s;
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if (FULL_SYSTEM) {
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if (FullSystem) {
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if (isCoprocessor0Enabled(xc)) {
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if(isMMUTLB(xc)){
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%(code)s;
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@ -176,7 +176,7 @@ output exec {{
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bool
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isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
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{
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if (!FULL_SYSTEM)
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if (!FullSystem)
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return true;
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MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
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@ -198,7 +198,7 @@ output exec {{
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bool inline
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isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
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MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
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// In Stat, EXL, ERL or CU0 set, CP0 accessible
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@ -215,7 +215,7 @@ output exec {{
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isMMUTLB(%(CPU_exec_context)s *xc)
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{
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MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
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return FULL_SYSTEM && (Config & 0x380) == 0x80;
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return FullSystem && (Config & 0x380) == 0x80;
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}
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}};
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@ -143,7 +143,7 @@ output exec {{
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bool
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isDspEnabled(%(CPU_exec_context)s *xc)
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{
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return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
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return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
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}
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}};
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@ -151,7 +151,7 @@ output exec {{
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bool
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isDspPresent(%(CPU_exec_context)s *xc)
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{
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return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
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return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
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}
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}};
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@ -174,7 +174,7 @@ def template FloatingPointExecute {{
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//When is the right time to reset cause bits?
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//start of every instruction or every cycle?
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if (FULL_SYSTEM)
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if (FullSystem)
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fpResetCauseBits(xc);
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%(op_decl)s;
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%(op_rd)s;
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@ -191,7 +191,7 @@ def template FloatingPointExecute {{
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//Check for IEEE 754 FP Exceptions
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//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
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bool invalid_op = false;
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if (FULL_SYSTEM) {
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if (FullSystem) {
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invalid_op =
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fpInvalidOp((FPOp*)this, xc, Fd, traceData);
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}
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@ -193,7 +193,7 @@ output exec {{
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CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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if (!isCoprocessorEnabled(xc, 0))
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return new CoprocessorUnusableFault(0);
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else
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@ -210,7 +210,7 @@ output exec {{
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CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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if (!isCoprocessorEnabled(xc, 1))
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return new CoprocessorUnusableFault(1);
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else
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CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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if (!isCoprocessorEnabled(xc, 2))
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return new CoprocessorUnusableFault(2);
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else
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@ -58,6 +58,7 @@ output decoder {{
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#include "base/cprintf.hh"
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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#include "sim/full_system.hh"
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#if defined(linux)
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#include <fenv.h>
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#endif
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@ -90,6 +91,7 @@ output exec {{
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/eventq.hh"
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#include "sim/full_system.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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@ -566,7 +566,7 @@ output exec {{
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static inline Fault
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checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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if (FULL_SYSTEM) {
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if (FullSystem) {
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if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
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xc->readMiscReg(MISCREG_FPRS) & 0x4) {
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return NoFault;
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@ -74,6 +74,7 @@ output exec {{
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#include "debug/Sparc.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/full_system.hh"
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#include "sim/pseudo_inst.hh"
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#include "sim/sim_exit.hh"
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@ -394,7 +394,7 @@
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default: Inst::RET_FAR();
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}
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0x4: int3();
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0x5: decode FULL_SYSTEM default int_Ib() {
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0x5: decode FullSystem default int_Ib() {
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0: decode IMMEDIATE {
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// Really only the LSB matters, but the predecoder
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// will sign extend it, and there's no easy way to
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@ -216,7 +216,7 @@
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default: Inst::UD2();
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}
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}
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0x05: decode FULL_SYSTEM {
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0x05: decode FullSystem {
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0: SyscallInst::syscall('xc->syscall(Rax)',
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IsSyscall, IsNonSpeculative, IsSerializeAfter);
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default: decode MODE_MODE {
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@ -398,7 +398,7 @@
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0x1: Inst::RDTSC();
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0x2: Inst::RDMSR();
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0x3: rdpmc();
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0x4: decode FULL_SYSTEM {
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0x4: decode FullSystem {
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0: SyscallInst::sysenter('xc->syscall(Rax)',
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IsSyscall, IsNonSpeculative, IsSerializeAfter);
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default: sysenter();
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@ -84,6 +84,7 @@ output decoder {{
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#include "base/misc.hh"
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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#include "mem/packet.hh"
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#include "sim/full_system.hh"
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#if defined(linux) || defined(__APPLE__)
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#include <fenv.h>
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