Daniel Johnson 09a6e424ec ARM: Implement numcpus bits in L2CTLR register.		2011-09-13 12:06:13 -05:00
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arch	ARM: Implement numcpus bits in L2CTLR register.	2011-09-13 12:06:13 -05:00
base	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
cpu	LSQ: Only trigger a memory violation with a load/load if the value changes.	2011-09-13 12:58:08 -04:00
dev	ARM: Add VExpress_E support with PCIe to gem5	2011-08-19 15:08:08 -05:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00
mem	Prefetch: Don't prefetch if address is in the write queue.	2011-09-13 12:06:13 -05:00
python	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
sim	LSQ: Only trigger a memory violation with a load/load if the value changes.	2011-09-13 12:58:08 -04:00
unittest	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00