sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

scons: rename TraceFlags to DebugFlags

Browse source
This commit is contained in:
Nathan Binkert 2011-06-02 17:36:21 -07:00
parent f49f384fe4
commit 2b1aa35e20
30 changed files with 185 additions and 187 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/SConscript
View file

@ -270,7 +270,6 @@ def DebugFlag(name, desc=None):
if name in debug_flags:
raise AttributeError, "Flag %s already specified" % name
debug_flags[name] = (name, (), desc)
TraceFlag = DebugFlag
def CompoundFlag(name, flags, desc=None):
if name in debug_flags:
@ -280,7 +279,6 @@ def CompoundFlag(name, flags, desc=None):
debug_flags[name] = (name, compound, desc)
Export('DebugFlag')
Export('TraceFlag')
Export('CompoundFlag')
########################################################################

6
src/arch/SConscript
View file

@ -126,7 +126,7 @@ isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
TraceFlag('IntRegs')
TraceFlag('FloatRegs')
TraceFlag('MiscRegs')
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
DebugFlag('MiscRegs')
CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])

8
src/arch/arm/SConscript
View file

@ -65,10 +65,10 @@ if env['TARGET_ISA'] == 'arm':
SimObject('ArmNativeTrace.py')
SimObject('ArmTLB.py')
TraceFlag('Arm')
TraceFlag('TLBVerbose')
TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
TraceFlag('Predecoder', "Instructions returned by the predecoder")
DebugFlag('Arm')
DebugFlag('TLBVerbose')
DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('Predecoder', "Instructions returned by the predecoder")
if env['FULL_SYSTEM']:
Source('interrupts.cc')
Source('stacktrace.cc')

2
src/arch/mips/SConscript
View file

@ -41,7 +41,7 @@ if env['TARGET_ISA'] == 'mips':
Source('dsp.cc')
SimObject('MipsTLB.py')
TraceFlag('MipsPRA')
DebugFlag('MipsPRA')
if env['FULL_SYSTEM']:
SimObject('MipsSystem.py')

2
src/arch/power/SConscript
View file

@ -45,7 +45,7 @@ if env['TARGET_ISA'] == 'power':
Source('utility.cc')
SimObject('PowerTLB.py')
TraceFlag('Power')
DebugFlag('Power')
if not env['FULL_SYSTEM']:
Source('process.cc')

4
src/arch/sparc/SConscript
View file

@ -44,8 +44,8 @@ if env['TARGET_ISA'] == 'sparc':
SimObject('SparcNativeTrace.py')
SimObject('SparcTLB.py')
TraceFlag('Sparc', "Generic SPARC ISA stuff")
TraceFlag('RegisterWindows', "Register window manipulation")
DebugFlag('Sparc', "Generic SPARC ISA stuff")
DebugFlag('RegisterWindows', "Register window manipulation")
if env['FULL_SYSTEM']:
SimObject('SparcSystem.py')

10
src/arch/x86/SConscript
View file

@ -66,14 +66,14 @@ if env['TARGET_ISA'] == 'x86':
SimObject('X86NativeTrace.py')
SimObject('X86TLB.py')
TraceFlag('Predecoder', "Predecoder debug output")
TraceFlag('X86', "Generic X86 ISA debugging")
DebugFlag('Predecoder', "Predecoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
if env['FULL_SYSTEM']:
TraceFlag('LocalApic', "Local APIC debugging")
TraceFlag('PageTableWalker', \
DebugFlag('LocalApic', "Local APIC debugging")
DebugFlag('PageTableWalker', \
"Page table walker state machine debugging")
TraceFlag('Faults', "Trace all faults/exceptions/traps")
DebugFlag('Faults', "Trace all faults/exceptions/traps")
SimObject('X86LocalApic.py')
SimObject('X86System.py')

24
src/base/SConscript
View file

@ -73,18 +73,18 @@ Source('loader/symtab.cc')
Source('stats/text.cc')
TraceFlag('Annotate', "State machine annotation debugging")
TraceFlag('AnnotateQ', "State machine annotation queue debugging")
TraceFlag('AnnotateVerbose', "Dump all state machine annotation details")
TraceFlag('GDBAcc', "Remote debugger accesses")
TraceFlag('GDBExtra', "Dump extra information on reads and writes")
TraceFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.")
TraceFlag('GDBRead', "Reads to the remote address space")
TraceFlag('GDBRecv', "Messages received from the remote application")
TraceFlag('GDBSend', "Messages sent to the remote application")
TraceFlag('GDBWrite', "Writes to the remote address space")
TraceFlag('SQL', "SQL queries sent to the server")
TraceFlag('StatEvents', "Statistics event tracking")
DebugFlag('Annotate', "State machine annotation debugging")
DebugFlag('AnnotateQ', "State machine annotation queue debugging")
DebugFlag('AnnotateVerbose', "Dump all state machine annotation details")
DebugFlag('GDBAcc', "Remote debugger accesses")
DebugFlag('GDBExtra', "Dump extra information on reads and writes")
DebugFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.")
DebugFlag('GDBRead', "Reads to the remote address space")
DebugFlag('GDBRecv', "Messages received from the remote application")
DebugFlag('GDBSend', "Messages sent to the remote application")
DebugFlag('GDBWrite', "Writes to the remote address space")
DebugFlag('SQL', "SQL queries sent to the server")
DebugFlag('StatEvents', "Statistics event tracking")
CompoundFlag('GDBAll',
[ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', 'GDBRecv',

2
src/base/vnc/SConscript
View file

@ -42,7 +42,7 @@ Import('*')
if env['FULL_SYSTEM']:
SimObject('VncServer.py')
Source('vncserver.cc')
TraceFlag('VNC')
DebugFlag('VNC')
Source('convert.cc')

54
src/cpu/SConscript
View file

@ -137,7 +137,7 @@ if env['FULL_SYSTEM']:
if env['USE_CHECKER']:
Source('checker/cpu.cc')
TraceFlag('Checker')
DebugFlag('Checker')
checker_supports = False
for i in CheckerSupportedCPUList:
if i in env['CPU_MODELS']:
@ -149,32 +149,32 @@ if env['USE_CHECKER']:
print ", please set USE_CHECKER=False or use one of those CPU models"
Exit(1)
TraceFlag('Activity')
TraceFlag('Commit')
TraceFlag('Context')
TraceFlag('Decode')
TraceFlag('DynInst')
TraceFlag('ExecEnable')
TraceFlag('ExecCPSeq')
TraceFlag('ExecEffAddr')
TraceFlag('ExecFaulting', 'Trace faulting instructions')
TraceFlag('ExecFetchSeq')
TraceFlag('ExecOpClass')
TraceFlag('ExecRegDelta')
TraceFlag('ExecResult')
TraceFlag('ExecSpeculative')
TraceFlag('ExecSymbol')
TraceFlag('ExecThread')
TraceFlag('ExecTicks')
TraceFlag('ExecMicro')
TraceFlag('ExecMacro')
TraceFlag('ExecUser')
TraceFlag('ExecKernel')
TraceFlag('ExecAsid')
TraceFlag('Fetch')
TraceFlag('IntrControl')
TraceFlag('PCEvent')
TraceFlag('Quiesce')
DebugFlag('Activity')
DebugFlag('Commit')
DebugFlag('Context')
DebugFlag('Decode')
DebugFlag('DynInst')
DebugFlag('ExecEnable')
DebugFlag('ExecCPSeq')
DebugFlag('ExecEffAddr')
DebugFlag('ExecFaulting', 'Trace faulting instructions')
DebugFlag('ExecFetchSeq')
DebugFlag('ExecOpClass')
DebugFlag('ExecRegDelta')
DebugFlag('ExecResult')
DebugFlag('ExecSpeculative')
DebugFlag('ExecSymbol')
DebugFlag('ExecThread')
DebugFlag('ExecTicks')
DebugFlag('ExecMicro')
DebugFlag('ExecMacro')
DebugFlag('ExecUser')
DebugFlag('ExecKernel')
DebugFlag('ExecAsid')
DebugFlag('Fetch')
DebugFlag('IntrControl')
DebugFlag('PCEvent')
DebugFlag('Quiesce')
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',

44
src/cpu/inorder/SConscript
View file

@ -34,28 +34,28 @@ if 'InOrderCPU' in env['CPU_MODELS']:
SimObject('InOrderCPU.py')
SimObject('InOrderTrace.py')
TraceFlag('ResReqCount')
TraceFlag('InOrderStage')
TraceFlag('InOrderStall')
TraceFlag('InOrderCPU')
TraceFlag('RegDepMap')
TraceFlag('InOrderDynInst')
TraceFlag('Resource')
TraceFlag('InOrderAGEN')
TraceFlag('InOrderFetchSeq')
TraceFlag('InOrderTLB')
TraceFlag('InOrderCachePort')
TraceFlag('InOrderBPred')
TraceFlag('InOrderDecode')
TraceFlag('InOrderExecute')
TraceFlag('InOrderInstBuffer')
TraceFlag('InOrderUseDef')
TraceFlag('InOrderMDU')
TraceFlag('InOrderGraduation')
TraceFlag('ThreadModel')
TraceFlag('RefCount')
TraceFlag('AddrDep')
TraceFlag('SkedCache')
DebugFlag('ResReqCount')
DebugFlag('InOrderStage')
DebugFlag('InOrderStall')
DebugFlag('InOrderCPU')
DebugFlag('RegDepMap')
DebugFlag('InOrderDynInst')
DebugFlag('Resource')
DebugFlag('InOrderAGEN')
DebugFlag('InOrderFetchSeq')
DebugFlag('InOrderTLB')
DebugFlag('InOrderCachePort')
DebugFlag('InOrderBPred')
DebugFlag('InOrderDecode')
DebugFlag('InOrderExecute')
DebugFlag('InOrderInstBuffer')
DebugFlag('InOrderUseDef')
DebugFlag('InOrderMDU')
DebugFlag('InOrderGraduation')
DebugFlag('ThreadModel')
DebugFlag('RefCount')
DebugFlag('AddrDep')
DebugFlag('SkedCache')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',

24
src/cpu/o3/SConscript
View file

@ -33,9 +33,9 @@ import sys
Import('*')
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
TraceFlag('CommitRate')
TraceFlag('IEW')
TraceFlag('IQ')
DebugFlag('CommitRate')
DebugFlag('IEW')
DebugFlag('IQ')
if 'O3CPU' in env['CPU_MODELS']:
SimObject('FUPool.py')
@ -64,15 +64,15 @@ if 'O3CPU' in env['CPU_MODELS']:
Source('store_set.cc')
Source('thread_context.cc')
TraceFlag('LSQ')
TraceFlag('LSQUnit')
TraceFlag('MemDepUnit')
TraceFlag('O3CPU')
TraceFlag('ROB')
TraceFlag('Rename')
TraceFlag('Scoreboard')
TraceFlag('StoreSet')
TraceFlag('Writeback')
DebugFlag('LSQ')
DebugFlag('LSQUnit')
DebugFlag('MemDepUnit')
DebugFlag('O3CPU')
DebugFlag('ROB')
DebugFlag('Rename')
DebugFlag('Scoreboard')
DebugFlag('StoreSet')
DebugFlag('Writeback')
CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',

10
src/cpu/ozone/SConscript
View file

@ -45,11 +45,11 @@ if 'OzoneCPU' in env['CPU_MODELS']:
Source('lw_lsq.cc')
Source('rename_table.cc')
TraceFlag('BE')
TraceFlag('FE')
TraceFlag('IBE')
TraceFlag('OzoneCPU')
TraceFlag('OzoneLSQ')
DebugFlag('BE')
DebugFlag('FE')
DebugFlag('IBE')
DebugFlag('OzoneCPU')
DebugFlag('OzoneLSQ')
CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])

2
src/cpu/pred/SConscript
View file

@ -35,4 +35,4 @@ if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
Source('btb.cc')
Source('ras.cc')
Source('tournament.cc')
TraceFlag('FreeList')
DebugFlag('FreeList')

2
src/cpu/simple/SConscript
View file

@ -43,7 +43,7 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']:
if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
'TimingSimpleCPU' in env['CPU_MODELS']:
TraceFlag('SimpleCPU')
DebugFlag('SimpleCPU')
if need_simple_base:
Source('base.cc')

2
src/cpu/testers/directedtest/SConscript
View file

@ -45,4 +45,4 @@ Source('DirectedGenerator.cc')
Source('SeriesRequestGenerator.cc')
Source('InvalidateGenerator.cc')
TraceFlag('DirectedTest')
DebugFlag('DirectedTest')

2
src/cpu/testers/memtest/SConscript
View file

@ -35,4 +35,4 @@ SimObject('MemTest.py')
Source('memtest.cc')
TraceFlag('MemTest')
DebugFlag('MemTest')

2
src/cpu/testers/networktest/SConscript
View file

@ -34,4 +34,4 @@ SimObject('NetworkTest.py')
Source('networktest.cc', Werror=False)
TraceFlag('NetworkTest')
DebugFlag('NetworkTest')

2
src/cpu/testers/rubytest/SConscript
View file

@ -44,4 +44,4 @@ Source('RubyTester.cc')
Source('Check.cc')
Source('CheckTable.cc')
TraceFlag('RubyTest')
DebugFlag('RubyTest')

50
src/dev/SConscript
View file

@ -76,31 +76,31 @@ if env['FULL_SYSTEM']:
Source('uart.cc')
Source('uart8250.cc')
TraceFlag('DiskImageRead')
TraceFlag('DiskImageWrite')
TraceFlag('DMA')
TraceFlag('DMACopyEngine')
TraceFlag('Ethernet')
TraceFlag('EthernetCksum')
TraceFlag('EthernetDMA')
TraceFlag('EthernetData')
TraceFlag('EthernetDesc')
TraceFlag('EthernetEEPROM')
TraceFlag('EthernetIntr')
TraceFlag('EthernetPIO')
TraceFlag('EthernetSM')
TraceFlag('IdeCtrl')
TraceFlag('IdeDisk')
TraceFlag('Intel8254Timer')
TraceFlag('IsaFake')
TraceFlag('MC146818')
TraceFlag('PCIDEV')
TraceFlag('PciConfigAll')
TraceFlag('SimpleDisk')
TraceFlag('SimpleDiskData')
TraceFlag('Terminal')
TraceFlag('TerminalVerbose')
TraceFlag('Uart')
DebugFlag('DiskImageRead')
DebugFlag('DiskImageWrite')
DebugFlag('DMA')
DebugFlag('DMACopyEngine')
DebugFlag('Ethernet')
DebugFlag('EthernetCksum')
DebugFlag('EthernetDMA')
DebugFlag('EthernetData')
DebugFlag('EthernetDesc')
DebugFlag('EthernetEEPROM')
DebugFlag('EthernetIntr')
DebugFlag('EthernetPIO')
DebugFlag('EthernetSM')
DebugFlag('IdeCtrl')
DebugFlag('IdeDisk')
DebugFlag('Intel8254Timer')
DebugFlag('IsaFake')
DebugFlag('MC146818')
DebugFlag('PCIDEV')
DebugFlag('PciConfigAll')
DebugFlag('SimpleDisk')
DebugFlag('SimpleDiskData')
DebugFlag('Terminal')
DebugFlag('TerminalVerbose')
DebugFlag('Uart')
CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',

4
src/dev/alpha/SConscript
View file

@ -41,5 +41,5 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
Source('tsunami_io.cc')
Source('tsunami_pchip.cc')
TraceFlag('AlphaBackdoor')
TraceFlag('Tsunami')
DebugFlag('AlphaBackdoor')
DebugFlag('Tsunami')

8
src/dev/arm/SConscript
View file

@ -53,7 +53,7 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
Source('rv_ctrl.cc')
Source('realview.cc')
TraceFlag('AMBA')
TraceFlag('PL111')
TraceFlag('Pl050')
TraceFlag('GIC')
DebugFlag('AMBA')
DebugFlag('PL111')
DebugFlag('Pl050')
DebugFlag('GIC')

2
src/dev/mips/SConscript
View file

@ -34,7 +34,7 @@ Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
SimObject('Malta.py')
TraceFlag('Malta')
DebugFlag('Malta')
Source('malta.cc')
Source('malta_cchip.cc')

2
src/dev/sparc/SConscript
View file

@ -39,4 +39,4 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
Source('t1000.cc')
Source('mm_disk.cc')
TraceFlag('Iob')
DebugFlag('Iob')

16
src/dev/x86/SConscript
View file

@ -39,32 +39,32 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
SimObject('Cmos.py')
Source('cmos.cc')
TraceFlag('CMOS', 'Accesses to CMOS devices')
DebugFlag('CMOS', 'Accesses to CMOS devices')
SimObject('I8259.py')
Source('i8259.cc')
TraceFlag('I8259', 'Accesses to the I8259 PIC devices')
DebugFlag('I8259', 'Accesses to the I8259 PIC devices')
SimObject('I8254.py')
Source('i8254.cc')
TraceFlag('I8254', 'Interrupts from the I8254 timer');
DebugFlag('I8254', 'Interrupts from the I8254 timer');
SimObject('I8237.py')
Source('i8237.cc')
TraceFlag('I8237', 'The I8237 dma controller');
DebugFlag('I8237', 'The I8237 dma controller');
SimObject('I8042.py')
Source('i8042.cc')
TraceFlag('I8042', 'The I8042 keyboard controller');
DebugFlag('I8042', 'The I8042 keyboard controller');
SimObject('PcSpeaker.py')
Source('speaker.cc')
TraceFlag('PcSpeaker')
DebugFlag('PcSpeaker')
SimObject('I82094AA.py')
Source('i82094aa.cc')
TraceFlag('I82094AA')
DebugFlag('I82094AA')
SimObject('X86IntPin.py')
Source('intdev.cc')
TraceFlag('IntDev')
DebugFlag('IntDev')

6
src/kern/SConscript
View file

@ -37,8 +37,8 @@ if env['FULL_SYSTEM']:
Source('kernel_stats.cc')
Source('system_events.cc')
TraceFlag('DebugPrintf')
TraceFlag('Printf')
DebugFlag('DebugPrintf')
DebugFlag('Printf')
Source('linux/events.cc')
Source('linux/linux_syscalls.cc')
@ -49,7 +49,7 @@ if env['FULL_SYSTEM']:
Source('tru64/printf.cc')
Source('tru64/tru64_events.cc')
Source('tru64/tru64_syscalls.cc')
TraceFlag('BADADDR')
DebugFlag('BADADDR')
else:
Source('linux/linux.cc')
Source('operatingsystem.cc')

34
src/mem/SConscript
View file

@ -53,24 +53,24 @@ elif env['TARGET_ISA'] != 'no':
Source('page_table.cc')
Source('translating_port.cc')
TraceFlag('Bus')
TraceFlag('BusAddrRanges')
TraceFlag('BusBridge')
TraceFlag('LLSC')
TraceFlag('MMU')
TraceFlag('MemoryAccess')
DebugFlag('Bus')
DebugFlag('BusAddrRanges')
DebugFlag('BusBridge')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
TraceFlag('ProtocolTrace')
TraceFlag('RubyCache')
TraceFlag('RubyDma')
TraceFlag('RubyGenerated')
TraceFlag('RubyMemory')
TraceFlag('RubyNetwork')
TraceFlag('RubyPort')
TraceFlag('RubyQueue')
TraceFlag('RubySlicc')
TraceFlag('RubyStorebuffer')
TraceFlag('RubyTester')
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
DebugFlag('RubyDma')
DebugFlag('RubyGenerated')
DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
DebugFlag('RubyQueue')
DebugFlag('RubySlicc')
DebugFlag('RubyStorebuffer')
DebugFlag('RubyTester')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',

8
src/mem/cache/SConscript vendored
View file

@ -42,7 +42,7 @@ Source('builder.cc')
Source('mshr.cc')
Source('mshr_queue.cc')
TraceFlag('Cache')
TraceFlag('CachePort')
TraceFlag('CacheRepl')
TraceFlag('HWPrefetch')
DebugFlag('Cache')
DebugFlag('CachePort')
DebugFlag('CacheRepl')
DebugFlag('HWPrefetch')

4
src/mem/cache/tags/SConscript vendored
View file

@ -42,5 +42,5 @@ Source('cacheset.cc')
SimObject('iic_repl/Repl.py')
Source('iic_repl/gen.cc')
TraceFlag('IIC')
TraceFlag('IICMore')
DebugFlag('IIC')
DebugFlag('IICMore')

34
src/sim/SConscript
View file

@ -62,20 +62,20 @@ elif env['TARGET_ISA'] != 'no':
Source('process.cc')
Source('syscall_emul.cc')
TraceFlag('Checkpoint')
TraceFlag('Config')
TraceFlag('Event')
TraceFlag('Fault')
TraceFlag('Flow')
TraceFlag('IPI')
TraceFlag('IPR')
TraceFlag('Interrupt')
TraceFlag('Loader')
TraceFlag('Stack')
TraceFlag('SyscallVerbose')
TraceFlag('TimeSync')
TraceFlag('TLB')
TraceFlag('Thread')
TraceFlag('Timer')
TraceFlag('VtoPhys')
TraceFlag('WorkItems')
DebugFlag('Checkpoint')
DebugFlag('Config')
DebugFlag('Event')
DebugFlag('Fault')
DebugFlag('Flow')
DebugFlag('IPI')
DebugFlag('IPR')
DebugFlag('Interrupt')
DebugFlag('Loader')
DebugFlag('Stack')
DebugFlag('SyscallVerbose')
DebugFlag('TimeSync')
DebugFlag('TLB')
DebugFlag('Thread')
DebugFlag('Timer')
DebugFlag('VtoPhys')
DebugFlag('WorkItems')