ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
This commit is contained in:
Ali Saidi
parent
3876105bdb
commit
91b737ed48
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@ -252,6 +252,9 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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self.realview = RealViewEB()
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elif machine_type == "VExpress_ELT":
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self.realview = VExpress_ELT()
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elif machine_type == "VExpress_EMM":
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self.realview = VExpress_EMM()
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self.load_addr_mask = 0xffffffff
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else:
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print "Unknown Machine Type"
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sys.exit(1)
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@ -273,21 +276,17 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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else:
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self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
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self.machine_type = machine_type
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if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
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print "The currently implemented ARM platforms only easily support 256MB of DRAM"
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print "It might be possible to get some more by using 256MB@0x30000000, but this"
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print "is untested and may require some heroics"
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if convert.toMemorySize(mdesc.mem()) > self.realview.max_mem_size:
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print "The currently selected ARM platforms doesn't support"
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print " the amount of DRAM you've selected. Please try"
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print " another platform"
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boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
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'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
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self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
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zero = True)
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self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
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size = '64MB'), zero = True)
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self.nvmem.port = self.membus.master
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self.boot_loader = binary('boot.arm')
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self.boot_loader_mem = self.nvmem
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self.physmem = PhysicalMemory(range = AddrRange(self.realview.mem_start_addr,
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size = mdesc.mem()))
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self.realview.setupBootLoader(self.membus, self, binary)
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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@ -159,12 +159,12 @@ if bm[0]:
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else:
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mem_size = SysConfig().mem()
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if options.caches or options.l2cache:
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test_sys.iocache = IOCache(addr_range=mem_size)
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test_sys.iocache = IOCache(addr_range=test_sys.physmem.range)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
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ranges = [AddrRange(mem_size)])
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ranges = [test_sys.physmem.range])
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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@ -195,7 +195,7 @@ if len(bm) == 2:
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if options.kernel is not None:
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drive_sys.kernel = binary(options.kernel)
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drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
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ranges = [AddrRange(bm[1].mem())])
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ranges = [drive_sys.physmem.range])
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drive_sys.iobridge.slave = drive_sys.iobus.master
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drive_sys.iobridge.master = drive_sys.membus.slave
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@ -43,7 +43,8 @@ class ArmMachineType(Enum):
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map = {'RealView_EB' : 827,
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'RealView_PBX' : 1901,
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'VExpress_ELT' : 2272,
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'VExpress_CA9' : 2272}
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'VExpress_CA9' : 2272,
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'VExpress_EMM' : 2272}
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class ArmSystem(System):
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type = 'ArmSystem'
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@ -65,5 +66,6 @@ class LinuxArmSystem(ArmSystem):
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load_addr_mask = 0x0fffffff
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machine_type = Param.ArmMachineType('RealView_PBX',
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"Machine id from http://www.arm.linux.org.uk/developer/machines/")
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atags_addr = Param.Addr(0x100, "Address where default atags structure should be written")
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@ -213,8 +213,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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"config registers and jumping to ThumbEE vectors\n");
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return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
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case MISCREG_ID_PFR1:
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warn("reading unimplmented register ID_PFR1");
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return 0;
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return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
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case MISCREG_CTR:
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return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
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case MISCREG_ACTLR:
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@ -114,7 +114,7 @@ LinuxArmSystem::initState()
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DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
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DDUMP(Loader, boot_data, size << 2);
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physProxy.writeBlob(ParamsList, boot_data, size << 2);
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physProxy.writeBlob(params()->atags_addr, boot_data, size << 2);
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#ifndef NDEBUG
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kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
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@ -154,7 +154,7 @@ LinuxArmSystem::initState()
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for (int i = 0; i < threadContexts.size(); i++) {
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threadContexts[i]->setIntReg(0, 0);
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threadContexts[i]->setIntReg(1, params()->machine_type);
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threadContexts[i]->setIntReg(2, ParamsList);
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threadContexts[i]->setIntReg(2, params()->atags_addr);
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}
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}
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@ -52,9 +52,6 @@
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class LinuxArmSystem : public ArmSystem
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{
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protected:
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static const int ParamsList = 0x100;
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public:
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/** Boilerplate params code */
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typedef LinuxArmSystemParams Params;
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@ -1,4 +1,4 @@
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# Copyright (c) 2009-2011 ARM Limited
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# Copyright (c) 2009-2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -49,6 +49,7 @@ from Ide import *
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from Platform import Platform
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from Terminal import Terminal
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from Uart import Uart
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from PhysicalMemory import *
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class AmbaDevice(BasicPioDevice):
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type = 'AmbaDevice'
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@ -119,6 +120,11 @@ class CpuLocalTimer(BasicPioDevice):
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int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
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clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
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class PL031(AmbaIntDevice):
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type = 'PL031'
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time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
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amba_id = 0x00341031
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class Pl050(AmbaIntDevice):
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type = 'Pl050'
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vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
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@ -136,6 +142,15 @@ class RealView(Platform):
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type = 'RealView'
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system = Param.System(Parent.any, "system")
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pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
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mem_start_addr = Param.Addr(0, "Start address of main memory")
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max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), size = '64MB'), zero = True)
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = loc('boot.arm')
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cur_sys.boot_loader_mem = self.nvmem
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# Reference for memory map and interrupt number
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# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
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@ -189,7 +204,9 @@ class RealViewPBX(RealView):
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# (gic, l2x0, a9scu, local_cpu_timer)
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bridge.ranges = [AddrRange(self.realview_io.pio_addr,
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self.a9scu.pio_addr - 1),
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AddrRange(self.flash_fake.pio_addr, Addr.max)]
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AddrRange(self.flash_fake.pio_addr,
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self.flash_fake.pio_addr + \
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self.flash_fake.pio_size - 1)]
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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@ -300,6 +317,7 @@ class RealViewEB(RealView):
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self.smcreg_fake.pio = bus.master
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class VExpress_ELT(RealView):
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max_mem_size = '2GB'
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pci_cfg_base = 0xD0000000
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elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
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uart = Pl011(pio_addr=0xFF009000, int_num=121)
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@ -402,3 +420,84 @@ class VExpress_ELT(RealView):
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self.lan_fake.pio = bus.master
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self.usb_fake.pio = bus.master
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class VExpress_EMM(RealView):
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mem_start_addr = '2GB'
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max_mem_size = '2GB'
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uart = Pl011(pio_addr=0x1c090000, int_num=37)
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realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
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gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000)
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local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
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timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='50MHz', clock1='50MHz')
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timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='50MHz', clock1='50MHz')
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clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
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kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
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kmi1 = Pl050(pio_addr=0x1c070000, int_num=45)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
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io_shift = 2, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0x1C1A0000, BAR0Size = '256B',
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BAR1 = 0x1C1A0100, BAR1Size = '4096B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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vram = PhysicalMemory(range = AddrRange(0x18000000, size='32MB'), zero = True)
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rtc = PL031(pio_addr=0x1C170000, int_num=36)
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l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
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uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
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uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
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uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
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sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
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watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
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aaci_fake = AmbaFake(pio_addr=0x1C040000)
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lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
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usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
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mmc_fake = AmbaFake(pio_addr=0x1c050000)
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = PhysicalMemory(range = AddrRange(0, size = '64MB'), zero = True)
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = loc('boot_emm.arm')
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cur_sys.boot_loader_mem = self.nvmem
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cur_sys.atags_addr = 0x80000100
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.local_cpu_timer.pio = bus.master
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, a9scu)
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bridge.ranges = [AddrRange(0x2F000000, size='16MB'),
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AddrRange(0x30000000, size='256MB'),
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AddrRange(0x40000000, size='512MB'),
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AddrRange(0x18000000, size='64MB'),
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AddrRange(0x1C000000, size='64MB')]
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.uart.pio = bus.master
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self.realview_io.pio = bus.master
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self.timer0.pio = bus.master
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self.timer1.pio = bus.master
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self.clcd.pio = bus.master
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self.clcd.dma = bus.slave
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self.kmi0.pio = bus.master
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self.kmi1.pio = bus.master
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self.cf_ctrl.pio = bus.master
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self.cf_ctrl.config = bus.master
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self.rtc.pio = bus.master
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bus.use_default_range = True
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self.vram.port = bus.master
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self.l2x0_fake.pio = bus.master
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self.uart1_fake.pio = bus.master
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self.uart2_fake.pio = bus.master
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self.uart3_fake.pio = bus.master
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self.sp810_fake.pio = bus.master
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self.watchdog_fake.pio = bus.master
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self.aaci_fake.pio = bus.master
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self.lan_fake.pio = bus.master
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self.usb_fake.pio = bus.master
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self.mmc_fake.pio = bus.master
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@ -103,6 +103,8 @@ RealViewCtrl::read(PacketPtr pkt)
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case IdReg:
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pkt->set<uint32_t>(params()->idreg);
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break;
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case CfgStat:
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pkt->set<uint32_t>(1);
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default:
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warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
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daddr);
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@ -40,21 +40,24 @@
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# Need to have CROSS_COMPILE set to /path/to/bin/arm-unknown-linux-gnu-
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# or have arm-unknown-linux-gnu in your path
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CROSS_COMPILE?=arm-none-linux-gnueabi-
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CROSS_COMPILE?=arm-linux-gnueabi-
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CC=$(CROSS_COMPILE)gcc
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CPP=$(CROSS_COMPILE)g++
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LD=$(CROSS_COMPILE)ld
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all: boot.arm
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all: boot.arm boot_emm.arm
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boot.o: simple.S
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$(CC) -mfloat-abi=softfp -march=armv7-a -fno-builtin -nostdinc -o boot.o -c simple.S
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$(CC) -mfloat-abi=softfp -march=armv7-a -fno-builtin -nostdinc -o $@ -c $<
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boot.arm: boot.o
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$(LD) -o boot.arm -N -Ttext 0x80000000 boot.o -non_shared -static
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$(LD) -o $@ -N -Ttext 0x80000000 $< -non_shared -static
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boot_emm.arm: boot.o
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$(LD) -o $@ -N -Ttext 0x00000010 $< -non_shared -static
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clean:
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rm *.o boot.arm
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$(RM) -f *.o boot.arm boot_emm.arm
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.PHONY: all clean
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