CP15 c15: enable execution with accesses to c15 registers

Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.
This commit is contained in:
Chander Sudanthi 2011-09-13 12:06:13 -05:00
parent 09a6e424ec
commit 7c479d7349
3 changed files with 6 additions and 1 deletions

View file

@ -143,6 +143,9 @@ let {{
case MISCREG_L2LATENCY:
return new WarnUnimplemented(
isRead ? "mrc l2latency" : "mcr l2latency", machInst);
case MISCREG_CRN15:
return new WarnUnimplemented(
isRead ? "mrc crn15" : "mcr crn15", machInst);
// Write only.
case MISCREG_TLBIALLIS:

View file

@ -463,7 +463,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
break;
case 15:
// Implementation defined
break;
return MISCREG_CRN15;
}
// Unrecognized register
return NUM_MISCREGS;

View file

@ -196,6 +196,7 @@ namespace ArmISA
MISCREG_ISR,
MISCREG_FCEIDR,
MISCREG_L2LATENCY,
MISCREG_CRN15,
MISCREG_CP15_END,
@ -249,6 +250,7 @@ namespace ArmISA
"dccmvau",
"nsacr",
"vbar", "mvbar", "isr", "fceidr", "l2latency",
"crn15",
"nop", "raz"
};