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X86: Turn on the page table walker in SE mode.

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This commit is contained in:
Gabe Black 2011-10-13 02:22:23 -07:00
parent 4b2e5ebead
commit 8adc6781bf
5 changed files with 50 additions and 55 deletions
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6
src/arch/x86/SConscript
View file

@ -57,6 +57,7 @@ if env['TARGET_ISA'] == 'x86':
Source('isa.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
Source('pagetable_walker.cc')
Source('predecoder.cc')
Source('predecoder_tables.cc')
Source('remote_gdb.cc')
@ -70,18 +71,17 @@ if env['TARGET_ISA'] == 'x86':
DebugFlag('Faults', "Trace all faults/exceptions/traps")
DebugFlag('LocalApic', "Local APIC debugging")
DebugFlag('PageTableWalker', \
"Page table walker state machine debugging")
DebugFlag('Predecoder', "Predecoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
if env['FULL_SYSTEM']:
DebugFlag('PageTableWalker', \
"Page table walker state machine debugging")
SimObject('X86System.py')
# Full-system sources
Source('linux/system.cc')
Source('pagetable_walker.cc')
Source('system.cc')
Source('stacktrace.cc')
Source('vtophys.cc')

17
src/arch/x86/X86TLB.py
View file

@ -35,24 +35,21 @@
#
# Authors: Gabe Black
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from BaseTLB import BaseTLB
from MemObject import MemObject
if buildEnv['FULL_SYSTEM']:
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
port = Port("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
port = Port("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
size = Param.Int(64, "TLB size")
if buildEnv['FULL_SYSTEM']:
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")

73
src/arch/x86/tlb.cc
View file

@ -44,6 +44,7 @@
#include "arch/x86/regs/msr.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
@ -55,13 +56,13 @@
#include "mem/packet_access.hh"
#include "mem/request.hh"
#if FULL_SYSTEM
#include "arch/x86/pagetable_walker.hh"
#else
#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
#endif
#include "sim/full_system.hh"
namespace X86ISA {
TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
@ -72,10 +73,8 @@ TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
for (int x = 0; x < size; x++)
freeList.push_back(&tlb[x]);
#if FULL_SYSTEM
walker = p->walker;
walker->setTLB(this);
#endif
}
TlbEntry *
@ -293,40 +292,42 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
if (!entry) {
#if FULL_SYSTEM
Fault fault = walker->start(tc, translation, req, mode);
if (timing || fault != NoFault) {
// This gets ignored in atomic mode.
delayedResponse = true;
return fault;
}
entry = lookup(vaddr);
assert(entry);
#else
DPRINTF(TLB, "Handling a TLB miss for "
"address %#x at pc %#x.\n",
vaddr, tc->instAddr());
Process *p = tc->getProcessPtr();
TlbEntry newEntry;
bool success = p->pTable->lookup(vaddr, newEntry);
if (!success && mode != Execute) {
// Check if we just need to grow the stack.
if (p->fixupStackFault(vaddr)) {
// If we did, lookup the entry for the new page.
success = p->pTable->lookup(vaddr, newEntry);
if (FullSystem) {
Fault fault = walker->start(tc, translation, req, mode);
if (timing || fault != NoFault) {
// This gets ignored in atomic mode.
delayedResponse = true;
return fault;
}
}
if (!success) {
return new PageFault(vaddr, true, mode, true, false);
entry = lookup(vaddr);
assert(entry);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
newEntry.pageStart());
entry = insert(alignedVaddr, newEntry);
}
DPRINTF(TLB, "Miss was serviced.\n");
#if !FULL_SYSTEM
DPRINTF(TLB, "Handling a TLB miss for "
"address %#x at pc %#x.\n",
vaddr, tc->instAddr());
Process *p = tc->getProcessPtr();
TlbEntry newEntry;
bool success = p->pTable->lookup(vaddr, newEntry);
if (!success && mode != Execute) {
// Check if we just need to grow the stack.
if (p->fixupStackFault(vaddr)) {
// If we did, lookup the entry for the new page.
success = p->pTable->lookup(vaddr, newEntry);
}
}
if (!success) {
return new PageFault(vaddr, true, mode, true, false);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
newEntry.pageStart());
entry = insert(alignedVaddr, newEntry);
}
DPRINTF(TLB, "Miss was serviced.\n");
#endif
}
}
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&

6
src/arch/x86/tlb.hh
View file

@ -85,15 +85,11 @@ namespace X86ISA
EntryList::iterator lookupIt(Addr va, bool update_lru = true);
#if FULL_SYSTEM
protected:
Walker * walker;
public:
Walker *getWalker();
#endif
public:
void invalidateAll();
void invalidateNonGlobal();

3
src/cpu/BaseCPU.py
View file

@ -140,7 +140,8 @@ class BaseCPU(MemObject):
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
_cached_ports = []
if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
if buildEnv['TARGET_ISA'] == 'x86' or \
(buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']):
_cached_ports = ["itb.walker.port", "dtb.walker.port"]
_uncached_ports = []