MEM: Prepare mport for master/slave split
This patch simplifies the mport in preparation for a split into a master and slave role for the message ports. In particular, sendMessageAtomic was only used in a single location and similarly so sendMessageTiming. The affected interrupt device is updated accordingly.
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -31,17 +43,21 @@
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#include "dev/x86/intdev.hh"
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void
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X86ISA::IntDev::IntPort::sendMessage(ApicList apics,
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TriggerIntMessage message, bool timing)
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X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message,
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bool timing)
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{
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ApicList::iterator apicIt;
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for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
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PacketPtr pkt = buildIntRequest(*apicIt, message);
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if (timing) {
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sendMessageTiming(pkt, latency);
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schedSendTiming(pkt, curTick() + latency);
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// The target handles cleaning up the packet in timing mode.
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} else {
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sendMessageAtomic(pkt);
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// ignore the latency involved in the atomic transaction
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sendAtomic(pkt);
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assert(pkt->isResponse());
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// also ignore the latency in handling the response
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recvResponse(pkt);
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delete pkt->req;
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delete pkt;
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}
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -34,30 +46,14 @@ Tick
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MessagePort::recvAtomic(PacketPtr pkt)
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{
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if (pkt->cmd == MemCmd::MessageReq) {
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// We received a message.
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return recvMessage(pkt);
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} else if (pkt->cmd == MemCmd::MessageResp) {
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// normally we would never see responses in recvAtomic, but
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// since the timing port uses recvAtomic to implement
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// recvTiming we have to deal with both cases
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return recvResponse(pkt);
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} else if (pkt->wasNacked()) {
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return recvNack(pkt);
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} else if (pkt->isError()) {
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panic("Packet is error.\n");
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} else {
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panic("Unexpected memory command %s.\n", pkt->cmd.toString());
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panic("%s received unexpected atomic command %s from %s.\n",
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name(), pkt->cmd.toString(), getPeer()->name());
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}
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}
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void
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MessagePort::sendMessageTiming(PacketPtr pkt, Tick latency)
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{
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schedSendTiming(pkt, curTick() + latency);
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}
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Tick
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MessagePort::sendMessageAtomic(PacketPtr pkt)
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{
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Tick latency = sendAtomic(pkt);
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assert(pkt->isResponse());
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latency += recvResponse(pkt);
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return latency;
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}
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@ -59,6 +59,8 @@ class MessagePort : public SimpleTimingPort
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Tick recvAtomic(PacketPtr pkt);
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protected:
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virtual Tick recvMessage(PacketPtr pkt) = 0;
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// Accept and ignore responses.
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@ -66,15 +68,6 @@ class MessagePort : public SimpleTimingPort
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{
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return 0;
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}
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// Since by default we're assuming everything we send is accepted, panic.
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virtual Tick recvNack(PacketPtr pkt)
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{
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panic("Unhandled message nack.\n");
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}
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void sendMessageTiming(PacketPtr pkt, Tick latency);
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Tick sendMessageAtomic(PacketPtr pkt);
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};
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#endif
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