gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).

src/arch/alpha/isa/main.isa

@@ -222,7 +222,7 @@ output header {{
         /// this class and derived classes.  Maybe these should really
         /// live here and not in the AlphaISA namespace.
         enum DependenceTags {
-            FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
+            FP_Base_DepTag = AlphaISA::FP_Base_DepTag
         };
 
         /// Constructor.

src/arch/alpha/isa_traits.hh

@@ -119,7 +119,7 @@ enum {
     MachineBytes = 8,
     WordBytes = 4,
     HalfwordBytes = 2,
-    ByteBytes = 1,
+    ByteBytes = 1
 };
 
 // return a no-op instruction... used for instruction fetch faults

src/arch/alpha/types.hh

@@ -48,7 +48,7 @@ enum annotes
 {
     ANNOTE_NONE = 0,
     // An impossible number for instruction annotations
-    ITOUCH_ANNOTE = 0xffffffff,
+    ITOUCH_ANNOTE = 0xffffffff
 };
 
 } // namespace AlphaISA

src/arch/arm/intregs.hh

@@ -239,7 +239,7 @@ enum IntRegIndex
     INTREG_R6_FIQ = INTREG_R6,
     INTREG_R7_FIQ = INTREG_R7,
     INTREG_PC_FIQ = INTREG_PC,
-    INTREG_R15_FIQ = INTREG_R15,
+    INTREG_R15_FIQ = INTREG_R15
 };
 
 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];

src/arch/arm/isa/templates/neon.isa

@@ -234,12 +234,16 @@ def template NeonEqualRegExecute {{
 }};
 
 output header {{
-    uint16_t nextBiggerType(uint8_t);
-    uint32_t nextBiggerType(uint16_t);
-    uint64_t nextBiggerType(uint32_t);
-    int16_t nextBiggerType(int8_t);
-    int32_t nextBiggerType(int16_t);
-    int64_t nextBiggerType(int32_t);
+        template <typename T>
+            struct bigger_type_t;
+
+        template<> struct bigger_type_t<uint8_t> { typedef uint16_t type; };
+        template<> struct bigger_type_t<uint16_t> { typedef uint32_t type; };
+        template<> struct bigger_type_t<uint32_t> { typedef uint64_t type; };
+
+        template<> struct bigger_type_t<int8_t> { typedef int16_t type; };
+        template<> struct bigger_type_t<int16_t> { typedef int32_t type; };
+        template<> struct bigger_type_t<int32_t> { typedef int64_t type; };
 }};
 
 def template NeonUnequalRegExecute {{
@@ -247,7 +251,7 @@ def template NeonUnequalRegExecute {{
     Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
             Trace::InstRecord *traceData) const
     {
-        typedef typeof(nextBiggerType((Element)0)) BigElement;
+        typedef typename bigger_type_t<Element>::type BigElement;
         Fault fault = NoFault;
         %(op_decl)s;
         %(op_rd)s;

src/arch/arm/linux/atag.hh

@@ -51,7 +51,7 @@ enum {
     RevTag    = 0x54410007,
     SerialTag = 0x54410006,
     CmdTag    = 0x54410009,
-    NoneTag   = 0x00000000,
+    NoneTag   = 0x00000000
 };
 
 class AtagHeader

src/arch/arm/miscregs.cc

@@ -499,4 +499,4 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
     return NUM_MISCREGS;
 }
 
-};
+}

src/arch/arm/miscregs.hh

@@ -529,6 +529,6 @@ namespace ArmISA
       Bitfield<31>    l2rstDISABLE_monitor;
    EndBitUnion(L2CTLR)
 
-};
+}
 
 #endif // __ARCH_ARM_MISCREGS_HH__

src/arch/arm/nativetrace.cc

@@ -226,4 +226,4 @@ Trace::ArmNativeTrace *
 ArmNativeTraceParams::create()
 {
     return new Trace::ArmNativeTrace(this);
-};
+}

src/arch/arm/pagetable.hh

@@ -208,6 +208,6 @@ struct TlbEntry
 
 
 
-};
+}
 #endif // __ARCH_ARM_PAGETABLE_H__
 

src/arch/arm/predecoder.hh

@@ -149,6 +149,6 @@ namespace ArmISA
             return thisEmi;
         }
     };
-};
+}
 
 #endif // __ARCH_ARM_PREDECODER_HH__

src/arch/arm/table_walker.hh

@@ -325,7 +325,7 @@ class TableWalker : public MemObject
 
     /** Queue of requests that have passed are waiting because the walker is
      * currently busy. */
-    std::list<WalkerState *> pendingQueue;;
+    std::list<WalkerState *> pendingQueue;
 
 
     /** Port to issue translation requests from */

src/arch/arm/utility.hh

@@ -182,6 +182,6 @@ getExecutingAsid(ThreadContext *tc)
     return tc->readMiscReg(MISCREG_CONTEXTIDR);
 }
 
-};
+}
 
 #endif

src/arch/arm/vtophys.hh

@@ -45,7 +45,7 @@ namespace ArmISA {
     Addr vtophys(Addr vaddr);
     Addr vtophys(ThreadContext *tc, Addr vaddr);
     bool virtvalid(ThreadContext *tc, Addr vaddr);
-};
+}
 
 #endif // __ARCH_ARM_VTOPHYS_H__
 

src/arch/x86/bios/e820.hh

@@ -77,6 +77,6 @@ namespace X86ISA
 
         void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
     };
-};
+}
 
 #endif // __ARCH_X86_BIOS_E820_HH__

src/arch/x86/emulenv.hh

@@ -71,6 +71,6 @@ namespace X86ISA
         void doModRM(const ExtMachInst & machInst);
         void setSeg(const ExtMachInst & machInst);
     };
-};
+}
 
 #endif // __ARCH_X86_TYPES_HH__

src/arch/x86/faults.hh

@@ -419,6 +419,6 @@ namespace X86ISA
             return true;
         }
     };
-};
+}
 
 #endif // __ARCH_X86_FAULTS_HH__

src/arch/x86/isa/macroop.isa

@@ -89,7 +89,7 @@ def template MacroDeclare {{
                 std::string
                 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
             };
-        };
+        }
 }};
 
 def template MacroDisassembly {{

src/arch/x86/isa_traits.hh

@@ -85,6 +85,6 @@ namespace X86ISA
         SixtyFourBitMode                // Behave as if we're in 64 bit
                                         // mode (this doesn't actually matter).
     };
-};
+}
 
 #endif // __ARCH_X86_ISATRAITS_HH__

src/arch/x86/locked_mem.hh

@@ -53,6 +53,6 @@ namespace X86ISA
     {
         return true;
     }
-};
+}
 
 #endif // __ARCH_X86_LOCKEDMEM_HH__

src/arch/x86/mmapped_ipr.hh

@@ -78,6 +78,6 @@ namespace X86ISA
         xc->setMiscReg(index, gtoh(data));
         return xc->getCpuPtr()->ticks(1);
     }
-};
+}
 
 #endif // __ARCH_X86_MMAPPEDIPR_HH__

src/arch/x86/nativetrace.cc

@@ -197,4 +197,4 @@ Trace::X86NativeTrace *
 X86NativeTraceParams::create()
 {
     return new Trace::X86NativeTrace(this);
-};
+}

src/arch/x86/predecoder.hh

@@ -234,6 +234,6 @@ namespace X86ISA
             return emi;
         }
     };
-};
+}
 
 #endif // __ARCH_X86_PREDECODER_HH__

src/arch/x86/regs/float.hh

@@ -150,6 +150,6 @@ namespace X86ISA
     {
         return FLOATREG_FPR((top + index + 8) % 8);
     }
-};
+}
 
 #endif // __ARCH_X86_FLOATREGS_HH__

src/arch/x86/regs/int.hh

@@ -178,6 +178,6 @@ namespace X86ISA
             index = (index - 4) | foldBit;
         return (IntRegIndex)index;
     }
-};
+}
 
 #endif // __ARCH_X86_INTREGS_HH__

src/arch/x86/regs/misc.hh

@@ -915,6 +915,6 @@ namespace X86ISA
         Bitfield<11> enable;
         Bitfield<8> bsp;
     EndBitUnion(LocalApicBase)
-};
+}
 
 #endif // __ARCH_X86_INTREGS_HH__

src/arch/x86/regs/segment.hh

@@ -63,6 +63,6 @@ namespace X86ISA
 
         NUM_SEGMENTREGS
     };
-};
+}
 
 #endif // __ARCH_X86_SEGMENTREGS_HH__

src/arch/x86/tlb.cc

@@ -384,7 +384,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
         }
     }
     return NoFault;
-};
+}
 
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)

src/arch/x86/types.hh

@@ -278,7 +278,7 @@ namespace X86ISA
         }
     };
 
-};
+}
 
 namespace __hash_namespace {
     template<>

src/arch/x86/utility.hh

@@ -105,6 +105,6 @@ namespace X86ISA
         return 0;
     }
 
-};
+}
 
 #endif // __ARCH_X86_UTILITY_HH__

src/arch/x86/vtophys.hh

@@ -50,6 +50,6 @@ namespace X86ISA
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
-};
+}
 
 #endif // __ARCH_X86_VTOPHYS_HH__

src/base/bitmap.cc

@@ -70,11 +70,13 @@ Bitmap::write(std::ostream *bmp) const
         // For further information see:
         //   http://en.wikipedia.org/wiki/BMP_file_format
         Magic magic = {{'B','M'}};
-        Header header = {sizeof(VideoConvert::Rgb8888) * width * height,
-                                0, 0, 54};
-        Info info = {sizeof(Info), width, height, 1,
-                    sizeof(VideoConvert::Rgb8888) * 8, 0,
-                    sizeof(VideoConvert::Rgb8888) * width * height, 1, 1, 0, 0};
+        Header header = {
+            static_cast<uint32_t>(sizeof(VideoConvert::Rgb8888)) *
+            width * height, 0, 0, 54};
+        Info info = {static_cast<uint32_t>(sizeof(Info)), width, height, 1,
+                     static_cast<uint32_t>(sizeof(VideoConvert::Rgb8888)) * 8,
+                     0, static_cast<uint32_t>(sizeof(VideoConvert::Rgb8888)) *
+                     width * height, 1, 1, 0, 0};
 
         char *p = headerBuffer = new char[sizeofHeaderBuffer];
         memcpy(p, &magic, sizeof(Magic));

src/base/callback.cc

@@ -28,7 +28,7 @@
  * Authors: Nathan Binkert
  */
 
-#import "base/callback.hh"
+#include "base/callback.hh"
 
 CallbackQueue::~CallbackQueue()
 {

src/base/range.cc

@@ -73,13 +73,13 @@ template<> bool \
 __parse_range(const std::string &s, type &first, type &last) \
 { return __x_parse_range(s, first, last); }
 
-RANGE_PARSE(unsigned long long);
-RANGE_PARSE(signed long long);
-RANGE_PARSE(unsigned long);
-RANGE_PARSE(signed long);
-RANGE_PARSE(unsigned int);
-RANGE_PARSE(signed int);
-RANGE_PARSE(unsigned short);
-RANGE_PARSE(signed short);
-RANGE_PARSE(unsigned char);
-RANGE_PARSE(signed char);
+RANGE_PARSE(unsigned long long)
+RANGE_PARSE(signed long long)
+RANGE_PARSE(unsigned long)
+RANGE_PARSE(signed long)
+RANGE_PARSE(unsigned int)
+RANGE_PARSE(signed int)
+RANGE_PARSE(unsigned short)
+RANGE_PARSE(signed short)
+RANGE_PARSE(unsigned char)
+RANGE_PARSE(signed char)

src/base/range_map.hh

@@ -32,6 +32,7 @@
 #define __BASE_RANGE_MAP_HH__
 
 #include <map>
+#include <utility>
 
 #include "base/range.hh"
 
@@ -95,7 +96,7 @@ class range_map
         if (intersect(r))
             return tree.end();
 
-        return tree.insert(std::make_pair<Range<T>,V>(r, d)).first;
+        return tree.insert(std::make_pair(r, d)).first;
     }
 
     size_t

src/base/str.cc

@@ -324,17 +324,17 @@ template<> \
 bool to_number<type>(const string &value, type &retval) \
 { return __to_number(value, retval); }
 
-STN(unsigned long long);
-STN(signed long long);
-STN(unsigned long);
-STN(signed long);
-STN(unsigned int);
-STN(signed int);
-STN(unsigned short);
-STN(signed short);
-STN(unsigned char);
-STN(signed char);
-STN(char);
+STN(unsigned long long)
+STN(signed long long)
+STN(unsigned long)
+STN(signed long)
+STN(unsigned int)
+STN(signed int)
+STN(unsigned short)
+STN(signed short)
+STN(unsigned char)
+STN(signed char)
+STN(char)
 
 template<>
 bool to_number<bool>(const string &value, bool &retval)

src/base/vnc/convert.hh

@@ -61,7 +61,7 @@ class VideoConvert
         bgr444,
         bgr4444,
         rgb444,
-        rgb4444,
+        rgb4444
     };
 
     // supports bpp32 RGB (bmp) and bpp16 5:6:5 mode BGR (linux)

src/cpu/base_dyn_inst.hh

@@ -96,7 +96,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
     /** The StaticInst used by this BaseDynInst. */

src/cpu/exetrace.cc

@@ -171,4 +171,4 @@ Trace::ExeTracer *
 ExeTracerParams::create()
 {
     return new Trace::ExeTracer(this);
-};
+}

src/cpu/inorder/inorder_dyn_inst.hh

@@ -103,7 +103,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
   public:

src/cpu/inorder/pipeline_traits.hh

@@ -77,7 +77,7 @@ namespace ThePipeline {
     //////////////////////////
     typedef ResourceSked ResSchedule;
     typedef ResourceSked* RSkedPtr;
-};
+}
 
 
 

src/cpu/inorder/resource.hh

@@ -263,7 +263,7 @@ class ResourceEvent : public Event
     /// (for InOrderCPU model).
     /// check src/sim/eventq.hh for more event priorities.
     enum InOrderPriority {
-        Resource_Event_Pri = 45,
+        Resource_Event_Pri = 45
     };
 
     /** The Resource Slot that this event is servicing */

src/cpu/inteltrace.cc

@@ -67,4 +67,4 @@ Trace::IntelTrace *
 IntelTraceParams::create()
 {
     return new Trace::IntelTrace(this);
-};
+}

src/cpu/o3/dyn_inst.hh

@@ -81,7 +81,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
   public:

src/cpu/o3/thread_context.hh

@@ -50,7 +50,7 @@
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
-};
+}
 
 /**
  * Derived ThreadContext class for use with the O3CPU.  It

src/cpu/simple_thread.hh

@@ -73,8 +73,8 @@ class ProfileNode;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * The SimpleThread object provides a combination of the ThreadState

src/cpu/static_inst.hh

@@ -87,7 +87,7 @@ class StaticInst : public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
     /// Set of boolean static instruction properties.

src/cpu/thread_context.hh

@@ -70,8 +70,8 @@ class System;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * ThreadContext is the external interface to all thread state for

src/cpu/thread_state.hh

@@ -45,8 +45,8 @@ class ProfileNode;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 class Checkpoint;
 

src/dev/i8254xGBe.hh

@@ -430,7 +430,7 @@ class IGbE : public EtherDevice
         Addr tsoMss;
         Addr tsoTotalLen;
         Addr tsoUsedLen;
-        Addr tsoPrevSeq;;
+        Addr tsoPrevSeq;
         Addr tsoPktPayloadBytes;
         bool tsoLoadedHeader;
         bool tsoPktHasHeader;

src/dev/ide_atareg.h

@@ -33,7 +33,7 @@
 #ifndef _DEV_ATA_ATAREG_H_
 #define _DEV_ATA_ATAREG_H_
 
-#if defined(linux)
+#if defined(__linux__)
 #include <endian.h>
 #elif defined(__sun)
 #include <sys/isa_defs.h>

src/dev/sinicreg.hh

@@ -31,8 +31,8 @@
 #ifndef __DEV_SINICREG_HH__
 #define __DEV_SINICREG_HH__
 
-#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
-#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
+#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
+#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
 
 #define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
         static const uint32_t NAME##_width = WIDTH; \
@@ -61,114 +61,114 @@ static const int VirtualShift = 8;
 static const int VirtualMask = 0xff;
 
 // Registers
-__SINIC_REG32(Config,        0x00); // 32: configuration register
-__SINIC_REG32(Command,       0x04); // 32: command register
-__SINIC_REG32(IntrStatus,    0x08); // 32: interrupt status
-__SINIC_REG32(IntrMask,      0x0c); // 32: interrupt mask
-__SINIC_REG32(RxMaxCopy,     0x10); // 32: max bytes per rx copy
-__SINIC_REG32(TxMaxCopy,     0x14); // 32: max bytes per tx copy
-__SINIC_REG32(ZeroCopySize,  0x18); // 32: bytes to copy if below threshold
-__SINIC_REG32(ZeroCopyMark,  0x1c); // 32: only zero-copy above this threshold
-__SINIC_REG32(VirtualCount,  0x20); // 32: number of virutal NICs
-__SINIC_REG32(RxMaxIntr,     0x24); // 32: max receives per interrupt
-__SINIC_REG32(RxFifoSize,    0x28); // 32: rx fifo capacity in bytes
-__SINIC_REG32(TxFifoSize,    0x2c); // 32: tx fifo capacity in bytes
-__SINIC_REG32(RxFifoLow,     0x30); // 32: rx fifo low watermark
-__SINIC_REG32(TxFifoLow,     0x34); // 32: tx fifo low watermark
-__SINIC_REG32(RxFifoHigh,    0x38); // 32: rx fifo high watermark
-__SINIC_REG32(TxFifoHigh,    0x3c); // 32: tx fifo high watermark
-__SINIC_REG32(RxData,        0x40); // 64: receive data
-__SINIC_REG32(RxDone,        0x48); // 64: receive done
-__SINIC_REG32(RxWait,        0x50); // 64: receive done (busy wait)
-__SINIC_REG32(TxData,        0x58); // 64: transmit data
-__SINIC_REG32(TxDone,        0x60); // 64: transmit done
-__SINIC_REG32(TxWait,        0x68); // 64: transmit done (busy wait)
-__SINIC_REG32(HwAddr,        0x70); // 64: mac address
-__SINIC_REG32(RxStatus,      0x78);
-__SINIC_REG32(Size,          0x80); // register addres space size
+__SINIC_REG32(Config,        0x00) // 32: configuration register
+__SINIC_REG32(Command,       0x04) // 32: command register
+__SINIC_REG32(IntrStatus,    0x08) // 32: interrupt status
+__SINIC_REG32(IntrMask,      0x0c) // 32: interrupt mask
+__SINIC_REG32(RxMaxCopy,     0x10) // 32: max bytes per rx copy
+__SINIC_REG32(TxMaxCopy,     0x14) // 32: max bytes per tx copy
+__SINIC_REG32(ZeroCopySize,  0x18) // 32: bytes to copy if below threshold
+__SINIC_REG32(ZeroCopyMark,  0x1c) // 32: only zero-copy above this threshold
+__SINIC_REG32(VirtualCount,  0x20) // 32: number of virutal NICs
+__SINIC_REG32(RxMaxIntr,     0x24) // 32: max receives per interrupt
+__SINIC_REG32(RxFifoSize,    0x28) // 32: rx fifo capacity in bytes
+__SINIC_REG32(TxFifoSize,    0x2c) // 32: tx fifo capacity in bytes
+__SINIC_REG32(RxFifoLow,     0x30) // 32: rx fifo low watermark
+__SINIC_REG32(TxFifoLow,     0x34) // 32: tx fifo low watermark
+__SINIC_REG32(RxFifoHigh,    0x38) // 32: rx fifo high watermark
+__SINIC_REG32(TxFifoHigh,    0x3c) // 32: tx fifo high watermark
+__SINIC_REG32(RxData,        0x40) // 64: receive data
+__SINIC_REG32(RxDone,        0x48) // 64: receive done
+__SINIC_REG32(RxWait,        0x50) // 64: receive done (busy wait)
+__SINIC_REG32(TxData,        0x58) // 64: transmit data
+__SINIC_REG32(TxDone,        0x60) // 64: transmit done
+__SINIC_REG32(TxWait,        0x68) // 64: transmit done (busy wait)
+__SINIC_REG32(HwAddr,        0x70) // 64: mac address
+__SINIC_REG32(RxStatus,      0x78)
+__SINIC_REG32(Size,          0x80) // register addres space size
 
 // Config register bits
-__SINIC_VAL32(Config_ZeroCopy, 12, 1); // enable zero copy
-__SINIC_VAL32(Config_DelayCopy,11, 1); // enable delayed copy
-__SINIC_VAL32(Config_RSS,      10, 1); // enable receive side scaling
-__SINIC_VAL32(Config_RxThread,  9, 1); // enable receive threads
-__SINIC_VAL32(Config_TxThread,  8, 1); // enable transmit thread
-__SINIC_VAL32(Config_Filter,    7, 1); // enable receive filter
-__SINIC_VAL32(Config_Vlan,      6, 1); // enable vlan tagging
-__SINIC_VAL32(Config_Vaddr,     5, 1); // enable virtual addressing
-__SINIC_VAL32(Config_Desc,      4, 1); // enable tx/rx descriptors
-__SINIC_VAL32(Config_Poll,      3, 1); // enable polling
-__SINIC_VAL32(Config_IntEn,     2, 1); // enable interrupts
-__SINIC_VAL32(Config_TxEn,      1, 1); // enable transmit
-__SINIC_VAL32(Config_RxEn,      0, 1); // enable receive
+__SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
+__SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
+__SINIC_VAL32(Config_RSS,      10, 1) // enable receive side scaling
+__SINIC_VAL32(Config_RxThread,  9, 1) // enable receive threads
+__SINIC_VAL32(Config_TxThread,  8, 1) // enable transmit thread
+__SINIC_VAL32(Config_Filter,    7, 1) // enable receive filter
+__SINIC_VAL32(Config_Vlan,      6, 1) // enable vlan tagging
+__SINIC_VAL32(Config_Vaddr,     5, 1) // enable virtual addressing
+__SINIC_VAL32(Config_Desc,      4, 1) // enable tx/rx descriptors
+__SINIC_VAL32(Config_Poll,      3, 1) // enable polling
+__SINIC_VAL32(Config_IntEn,     2, 1) // enable interrupts
+__SINIC_VAL32(Config_TxEn,      1, 1) // enable transmit
+__SINIC_VAL32(Config_RxEn,      0, 1) // enable receive
 
 // Command register bits
-__SINIC_VAL32(Command_Intr,  1, 1); // software interrupt
-__SINIC_VAL32(Command_Reset, 0, 1); // reset chip
+__SINIC_VAL32(Command_Intr,  1, 1) // software interrupt
+__SINIC_VAL32(Command_Reset, 0, 1) // reset chip
 
 // Interrupt register bits
-__SINIC_VAL32(Intr_Soft,      8, 1); // software interrupt
-__SINIC_VAL32(Intr_TxLow,     7, 1); // tx fifo dropped below watermark
-__SINIC_VAL32(Intr_TxFull,    6, 1); // tx fifo full
-__SINIC_VAL32(Intr_TxDMA,     5, 1); // tx dma completed w/ interrupt
-__SINIC_VAL32(Intr_TxPacket,  4, 1); // packet transmitted
-__SINIC_VAL32(Intr_RxHigh,    3, 1); // rx fifo above high watermark
-__SINIC_VAL32(Intr_RxEmpty,   2, 1); // rx fifo empty
-__SINIC_VAL32(Intr_RxDMA,     1, 1); // rx dma completed w/ interrupt
-__SINIC_VAL32(Intr_RxPacket,  0, 1); // packet received
-__SINIC_REG32(Intr_All,       0x01ff); // all valid interrupts
-__SINIC_REG32(Intr_NoDelay,   0x01cc); // interrupts that aren't coalesced
-__SINIC_REG32(Intr_Res,      ~0x01ff); // reserved interrupt bits
+__SINIC_VAL32(Intr_Soft,      8, 1) // software interrupt
+__SINIC_VAL32(Intr_TxLow,     7, 1) // tx fifo dropped below watermark
+__SINIC_VAL32(Intr_TxFull,    6, 1) // tx fifo full
+__SINIC_VAL32(Intr_TxDMA,     5, 1) // tx dma completed w/ interrupt
+__SINIC_VAL32(Intr_TxPacket,  4, 1) // packet transmitted
+__SINIC_VAL32(Intr_RxHigh,    3, 1) // rx fifo above high watermark
+__SINIC_VAL32(Intr_RxEmpty,   2, 1) // rx fifo empty
+__SINIC_VAL32(Intr_RxDMA,     1, 1) // rx dma completed w/ interrupt
+__SINIC_VAL32(Intr_RxPacket,  0, 1) // packet received
+__SINIC_REG32(Intr_All,       0x01ff) // all valid interrupts
+__SINIC_REG32(Intr_NoDelay,   0x01cc) // interrupts that aren't coalesced
+__SINIC_REG32(Intr_Res,      ~0x01ff) // reserved interrupt bits
 
 // RX Data Description
-__SINIC_VAL64(RxData_NoDelay,  61,  1); // Don't Delay this copy
-__SINIC_VAL64(RxData_Vaddr,    60,  1); // Addr is virtual
-__SINIC_VAL64(RxData_Len,      40, 20); // 0 - 256k
-__SINIC_VAL64(RxData_Addr,      0, 40); // Address 1TB
+__SINIC_VAL64(RxData_NoDelay,  61,  1) // Don't Delay this copy
+__SINIC_VAL64(RxData_Vaddr,    60,  1) // Addr is virtual
+__SINIC_VAL64(RxData_Len,      40, 20) // 0 - 256k
+__SINIC_VAL64(RxData_Addr,      0, 40) // Address 1TB
 
 // TX Data Description
-__SINIC_VAL64(TxData_More,     63,  1); // Packet not complete (will dma more)
-__SINIC_VAL64(TxData_Checksum, 62,  1); // do checksum
-__SINIC_VAL64(TxData_Vaddr,    60,  1); // Addr is virtual
-__SINIC_VAL64(TxData_Len,      40, 20); // 0 - 256k
-__SINIC_VAL64(TxData_Addr,      0, 40); // Address 1TB
+__SINIC_VAL64(TxData_More,     63,  1) // Packet not complete (will dma more)
+__SINIC_VAL64(TxData_Checksum, 62,  1) // do checksum
+__SINIC_VAL64(TxData_Vaddr,    60,  1) // Addr is virtual
+__SINIC_VAL64(TxData_Len,      40, 20) // 0 - 256k
+__SINIC_VAL64(TxData_Addr,      0, 40) // Address 1TB
 
 // RX Done/Busy Information
-__SINIC_VAL64(RxDone_Packets,   32, 16); // number of packets in rx fifo
-__SINIC_VAL64(RxDone_Busy,      31,  1); // receive dma busy copying
-__SINIC_VAL64(RxDone_Complete,  30,  1); // valid data (packet complete)
-__SINIC_VAL64(RxDone_More,      29,  1); // Packet has more data (dma again)
-__SINIC_VAL64(RxDone_Empty,     28,  1); // rx fifo is empty
-__SINIC_VAL64(RxDone_High,      27,  1); // rx fifo is above the watermark
-__SINIC_VAL64(RxDone_NotHigh,   26,  1); // rxfifo never hit the high watermark
-__SINIC_VAL64(RxDone_TcpError,  25,  1); // TCP packet error (bad checksum)
-__SINIC_VAL64(RxDone_UdpError,  24,  1); // UDP packet error (bad checksum)
-__SINIC_VAL64(RxDone_IpError,   23,  1); // IP packet error (bad checksum)
-__SINIC_VAL64(RxDone_TcpPacket, 22,  1); // this is a TCP packet
-__SINIC_VAL64(RxDone_UdpPacket, 21,  1); // this is a UDP packet
-__SINIC_VAL64(RxDone_IpPacket,  20,  1); // this is an IP packet
-__SINIC_VAL64(RxDone_CopyLen,    0, 20); // up to 256k
+__SINIC_VAL64(RxDone_Packets,   32, 16) // number of packets in rx fifo
+__SINIC_VAL64(RxDone_Busy,      31,  1) // receive dma busy copying
+__SINIC_VAL64(RxDone_Complete,  30,  1) // valid data (packet complete)
+__SINIC_VAL64(RxDone_More,      29,  1) // Packet has more data (dma again)
+__SINIC_VAL64(RxDone_Empty,     28,  1) // rx fifo is empty
+__SINIC_VAL64(RxDone_High,      27,  1) // rx fifo is above the watermark
+__SINIC_VAL64(RxDone_NotHigh,   26,  1) // rxfifo never hit the high watermark
+__SINIC_VAL64(RxDone_TcpError,  25,  1) // TCP packet error (bad checksum)
+__SINIC_VAL64(RxDone_UdpError,  24,  1) // UDP packet error (bad checksum)
+__SINIC_VAL64(RxDone_IpError,   23,  1) // IP packet error (bad checksum)
+__SINIC_VAL64(RxDone_TcpPacket, 22,  1) // this is a TCP packet
+__SINIC_VAL64(RxDone_UdpPacket, 21,  1) // this is a UDP packet
+__SINIC_VAL64(RxDone_IpPacket,  20,  1) // this is an IP packet
+__SINIC_VAL64(RxDone_CopyLen,    0, 20) // up to 256k
 
 // TX Done/Busy Information
-__SINIC_VAL64(TxDone_Packets,   32, 16); // number of packets in tx fifo
-__SINIC_VAL64(TxDone_Busy,      31,  1); // transmit dma busy copying
-__SINIC_VAL64(TxDone_Complete,  30,  1); // valid data (packet complete)
-__SINIC_VAL64(TxDone_Full,      29,  1); // tx fifo is full
-__SINIC_VAL64(TxDone_Low,       28,  1); // tx fifo is below the watermark
-__SINIC_VAL64(TxDone_Res0,      27,  1); // reserved
-__SINIC_VAL64(TxDone_Res1,      26,  1); // reserved
-__SINIC_VAL64(TxDone_Res2,      25,  1); // reserved
-__SINIC_VAL64(TxDone_Res3,      24,  1); // reserved
-__SINIC_VAL64(TxDone_Res4,      23,  1); // reserved
-__SINIC_VAL64(TxDone_Res5,      22,  1); // reserved
-__SINIC_VAL64(TxDone_Res6,      21,  1); // reserved
-__SINIC_VAL64(TxDone_Res7,      20,  1); // reserved
-__SINIC_VAL64(TxDone_CopyLen,    0, 20); // up to 256k
+__SINIC_VAL64(TxDone_Packets,   32, 16) // number of packets in tx fifo
+__SINIC_VAL64(TxDone_Busy,      31,  1) // transmit dma busy copying
+__SINIC_VAL64(TxDone_Complete,  30,  1) // valid data (packet complete)
+__SINIC_VAL64(TxDone_Full,      29,  1) // tx fifo is full
+__SINIC_VAL64(TxDone_Low,       28,  1) // tx fifo is below the watermark
+__SINIC_VAL64(TxDone_Res0,      27,  1) // reserved
+__SINIC_VAL64(TxDone_Res1,      26,  1) // reserved
+__SINIC_VAL64(TxDone_Res2,      25,  1) // reserved
+__SINIC_VAL64(TxDone_Res3,      24,  1) // reserved
+__SINIC_VAL64(TxDone_Res4,      23,  1) // reserved
+__SINIC_VAL64(TxDone_Res5,      22,  1) // reserved
+__SINIC_VAL64(TxDone_Res6,      21,  1) // reserved
+__SINIC_VAL64(TxDone_Res7,      20,  1) // reserved
+__SINIC_VAL64(TxDone_CopyLen,    0, 20) // up to 256k
 
-__SINIC_VAL64(RxStatus_Dirty,   48, 16);
-__SINIC_VAL64(RxStatus_Mapped,  32, 16);
-__SINIC_VAL64(RxStatus_Busy,    16, 16);
-__SINIC_VAL64(RxStatus_Head,     0, 16);
+__SINIC_VAL64(RxStatus_Dirty,   48, 16)
+__SINIC_VAL64(RxStatus_Mapped,  32, 16)
+__SINIC_VAL64(RxStatus_Busy,    16, 16)
+__SINIC_VAL64(RxStatus_Head,     0, 16)
 
 struct Info
 {

src/python/m5/params.py

@@ -1049,7 +1049,7 @@ namespace Enums {
         code.indent(2)
         for val in cls.vals:
             code('$val = ${{cls.map[val]}},')
-        code('Num_$name = ${{len(cls.vals)}},')
+        code('Num_$name = ${{len(cls.vals)}}')
         code.dedent(2)
         code('''\
     };

src/sim/byteswap.hh

@@ -42,7 +42,7 @@
 #include "base/types.hh"
 
 // This lets us figure out what the byte order of the host system is
-#if defined(linux)
+#if defined(__linux__)
 #include <endian.h>
 // If this is a linux system, lets used the optimized definitions if they exist.
 // If one doesn't exist, we pretty much get what is listed below, so it all
@@ -65,7 +65,7 @@ enum ByteOrder {BigEndianByteOrder, LittleEndianByteOrder};
 inline uint64_t
 swap_byte64(uint64_t x)
 {
-#if defined(linux)
+#if defined(__linux__)
     return bswap_64(x);
 #elif defined(__APPLE__)
     return OSSwapInt64(x);
@@ -84,7 +84,7 @@ swap_byte64(uint64_t x)
 inline uint32_t
 swap_byte32(uint32_t x)
 {
-#if defined(linux)
+#if defined(__linux__)
     return bswap_32(x);
 #elif defined(__APPLE__)
     return OSSwapInt32(x);
@@ -98,7 +98,7 @@ swap_byte32(uint32_t x)
 inline uint16_t
 swap_byte16(uint16_t x)
 {
-#if defined(linux)
+#if defined(__linux__)
     return bswap_16(x);
 #elif defined(__APPLE__)
     return OSSwapInt16(x);

src/sim/eventq.hh

@@ -66,7 +66,7 @@ class Event : public Serializable, public FastAlloc
     friend class EventQueue;
 
   protected:   
-    typedef short FlagsType;
+    typedef unsigned short FlagsType;
     typedef ::Flags<FlagsType> Flags;
 
     static const FlagsType PublicRead    = 0x003f; // public readable flags

src/sim/serialize.hh

@@ -89,6 +89,17 @@ void
 objParamIn(Checkpoint *cp, const std::string &section,
            const std::string &name, SimObject * &param);
 
+template <typename T>
+void fromInt(T &t, int i)
+{
+    t = (T)i;
+}
+
+template <typename T>
+void fromSimObject(T &t, SimObject *s)
+{
+    t = dynamic_cast<T>(s);
+}
 
 //
 // These macros are streamlined to use in serialize/unserialize
@@ -106,7 +117,7 @@ objParamIn(Checkpoint *cp, const std::string &section,
  do {                                           \
     int tmp;                                    \
     paramIn(cp, section, #scalar, tmp);         \
-    scalar = (typeof(scalar))tmp;               \
+    fromInt(scalar, tmp);                    \
   } while (0)
 
 #define SERIALIZE_ARRAY(member, size)           \
@@ -121,7 +132,7 @@ objParamIn(Checkpoint *cp, const std::string &section,
   do {                                                  \
     SimObject *sptr;                                    \
     objParamIn(cp, section, #objptr, sptr);             \
-    objptr = dynamic_cast<typeof(objptr)>(sptr);        \
+    fromSimObject(objptr, sptr);                        \
   } while (0)
 
 /*