PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
This commit is contained in:
parent
9eda6b1d88
commit
83aa47adca
6 changed files with 1 additions and 30 deletions
|
@ -944,7 +944,6 @@ decode OPCODE default Unknown::unknown() {
|
|||
format BasicOperate {
|
||||
// M5 special opcodes use the reserved 0x01 opcode space
|
||||
0x01: decode M5FUNC {
|
||||
#if FULL_SYSTEM
|
||||
0x00: arm({{
|
||||
PseudoInst::arm(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
|
@ -960,7 +959,6 @@ decode OPCODE default Unknown::unknown() {
|
|||
0x04: quiesceTime({{
|
||||
R0 = PseudoInst::quiesceTime(xc->tcBase());
|
||||
}}, IsNonSpeculative, IsUnverifiable);
|
||||
#endif
|
||||
0x07: rpns({{
|
||||
R0 = PseudoInst::rpns(xc->tcBase());
|
||||
}}, IsNonSpeculative, IsUnverifiable);
|
||||
|
@ -980,14 +978,12 @@ decode OPCODE default Unknown::unknown() {
|
|||
0x21: m5exit({{
|
||||
PseudoInst::m5exit(xc->tcBase(), R16);
|
||||
}}, No_OpClass, IsNonSpeculative);
|
||||
#if FULL_SYSTEM
|
||||
0x31: loadsymbol({{
|
||||
PseudoInst::loadsymbol(xc->tcBase());
|
||||
}}, No_OpClass, IsNonSpeculative);
|
||||
0x30: initparam({{
|
||||
Ra = PseudoInst::initParam(xc->tcBase());
|
||||
}});
|
||||
#endif
|
||||
0x40: resetstats({{
|
||||
PseudoInst::resetstats(xc->tcBase(), R16, R17);
|
||||
}}, IsNonSpeculative);
|
||||
|
@ -1000,22 +996,18 @@ decode OPCODE default Unknown::unknown() {
|
|||
0x43: m5checkpoint({{
|
||||
PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
|
||||
}}, IsNonSpeculative);
|
||||
#if FULL_SYSTEM
|
||||
0x50: m5readfile({{
|
||||
R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
|
||||
}}, IsNonSpeculative);
|
||||
#endif
|
||||
0x51: m5break({{
|
||||
PseudoInst::debugbreak(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
0x52: m5switchcpu({{
|
||||
PseudoInst::switchcpu(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
#if FULL_SYSTEM
|
||||
0x53: m5addsymbol({{
|
||||
PseudoInst::addsymbol(xc->tcBase(), R16, R17);
|
||||
}}, IsNonSpeculative);
|
||||
#endif
|
||||
0x54: m5panic({{
|
||||
panic("M5 panic instruction called at pc = %#x.", PC);
|
||||
}}, IsNonSpeculative);
|
||||
|
|
|
@ -196,9 +196,7 @@ def template QuiescePredOpExecute {{
|
|||
}
|
||||
} else {
|
||||
xc->setPredicate(false);
|
||||
#if FULL_SYSTEM
|
||||
PseudoInst::quiesceSkip(xc->tcBase());
|
||||
#endif
|
||||
}
|
||||
|
||||
return fault;
|
||||
|
@ -224,9 +222,7 @@ def template QuiescePredOpExecuteWithFixup {{
|
|||
} else {
|
||||
xc->setPredicate(false);
|
||||
%(pred_fixup)s;
|
||||
#if FULL_SYSTEM
|
||||
PseudoInst::quiesceSkip(xc->tcBase());
|
||||
#endif
|
||||
}
|
||||
|
||||
return fault;
|
||||
|
|
|
@ -975,7 +975,6 @@ decode OP default Unknown::unknown()
|
|||
}
|
||||
// M5 special opcodes use the reserved IMPDEP2A opcode space
|
||||
0x37: decode M5FUNC {
|
||||
#if FULL_SYSTEM
|
||||
format BasicOperate {
|
||||
// we have 7 bits of space here to play with...
|
||||
0x21: m5exit({{
|
||||
|
@ -991,7 +990,6 @@ decode OP default Unknown::unknown()
|
|||
panic("M5 panic instruction called at pc = %#x.", PC);
|
||||
}}, No_OpClass, IsNonSpeculative);
|
||||
}
|
||||
#endif
|
||||
default: Trap::impdep2({{fault = new IllegalInstruction;}});
|
||||
}
|
||||
0x38: Branch::jmpl({{
|
||||
|
|
|
@ -63,10 +63,6 @@ using namespace SparcISA;
|
|||
output exec {{
|
||||
#include "base/fenv.hh"
|
||||
|
||||
#if FULL_SYSTEM
|
||||
#include "sim/pseudo_inst.hh"
|
||||
#endif
|
||||
|
||||
#include <cmath>
|
||||
#include <limits>
|
||||
|
||||
|
@ -78,6 +74,7 @@ output exec {{
|
|||
#include "debug/Sparc.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/packet_access.hh"
|
||||
#include "sim/pseudo_inst.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
|
||||
using namespace SparcISA;
|
||||
|
|
|
@ -136,7 +136,6 @@
|
|||
//0x04: loadall_or_reset_or_hang();
|
||||
0x4: decode IMMEDIATE {
|
||||
format BasicOperate {
|
||||
#if FULL_SYSTEM
|
||||
0x00: m5arm({{
|
||||
PseudoInst::arm(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
|
@ -152,21 +151,18 @@
|
|||
0x04: m5quiesceTime({{
|
||||
Rax = PseudoInst::quiesceTime(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
#endif
|
||||
0x07: m5rpns({{
|
||||
Rax = PseudoInst::rpns(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
0x21: m5exit({{
|
||||
PseudoInst::m5exit(xc->tcBase(), Rdi);
|
||||
}}, IsNonSpeculative);
|
||||
#if FULL_SYSTEM
|
||||
0x30: m5initparam({{
|
||||
Rax = PseudoInst::initParam(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
0x31: m5loadsymbol({{
|
||||
PseudoInst::loadsymbol(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
#endif
|
||||
0x40: m5resetstats({{
|
||||
PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
|
||||
}}, IsNonSpeculative);
|
||||
|
@ -179,23 +175,19 @@
|
|||
0x43: m5checkpoint({{
|
||||
PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
|
||||
}}, IsNonSpeculative);
|
||||
#if FULL_SYSTEM
|
||||
0x50: m5readfile({{
|
||||
Rax = PseudoInst::readfile(
|
||||
xc->tcBase(), Rdi, Rsi, Rdx);
|
||||
}}, IsNonSpeculative);
|
||||
#endif
|
||||
0x51: m5debugbreak({{
|
||||
PseudoInst::debugbreak(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
0x52: m5switchcpu({{
|
||||
PseudoInst::switchcpu(xc->tcBase());
|
||||
}}, IsNonSpeculative);
|
||||
#if FULL_SYSTEM
|
||||
0x53: m5addsymbol({{
|
||||
PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
|
||||
}}, IsNonSpeculative);
|
||||
#endif
|
||||
0x54: m5panic({{
|
||||
panic("M5 panic instruction called at pc = %#x.\n",
|
||||
RIP);
|
||||
|
|
|
@ -102,10 +102,6 @@ output exec {{
|
|||
#include <ieeefp.h>
|
||||
#endif
|
||||
|
||||
#if FULL_SYSTEM
|
||||
#include "sim/pseudo_inst.hh"
|
||||
#endif
|
||||
|
||||
#include <cmath>
|
||||
#include <limits>
|
||||
|
||||
|
|
Loading…
Reference in a new issue