MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets rid of duplication, fixes some bugs, doubtlessly introduces others, and adds names for the exception code constants.
This commit is contained in:
Gabe Black
parent
4455fc484d
commit
9a38dc6194
2 changed files with 226 additions and 313 deletions
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@ -48,54 +48,56 @@ namespace MipsISA
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typedef MipsFaultBase::FaultVals FaultVals;
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template <> FaultVals MipsFault<MachineCheckFault>::vals =
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{ "Machine Check", 0x0401 };
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template <> FaultVals MipsFault<ResetFault>::vals =
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#if FULL_SYSTEM
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{ "Reset Fault", 0xBFC00000};
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#else
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{ "Reset Fault", 0x001};
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#endif
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template <> FaultVals MipsFault<AddressErrorFault>::vals =
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{ "Address Error", 0x0180 };
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template <> FaultVals MipsFault<SystemCallFault>::vals =
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{ "Syscall", 0x0180 };
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template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
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{ "Coprocessor Unusable Fault", 0x180 };
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{ "Syscall", 0x180, ExcCodeSys };
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template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
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{ "Reserved Instruction Fault", 0x0180 };
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{ "Reserved Instruction Fault", 0x180, ExcCodeRI };
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template <> FaultVals MipsFault<ThreadFault>::vals =
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{ "Thread Fault", 0x00F1 };
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{ "Thread Fault", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
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{ "Integer Overflow Exception", 0x180 };
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template <> FaultVals MipsFault<InterruptFault>::vals =
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{ "interrupt", 0x0180 };
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{ "Integer Overflow Exception", 0x180, ExcCodeOv };
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template <> FaultVals MipsFault<TrapFault>::vals =
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{ "Trap", 0x0180 };
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{ "Trap", 0x180, ExcCodeTr };
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template <> FaultVals MipsFault<BreakpointFault>::vals =
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{ "Breakpoint", 0x0180 };
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template <> FaultVals MipsFault<TlbInvalidFault>::vals =
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{ "Invalid TLB Entry Exception", 0x0180 };
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template <> FaultVals MipsFault<TlbRefillFault>::vals =
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{ "TLB Refill Exception", 0x0180 };
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template <> FaultVals MipsFault<TlbModifiedFault>::vals =
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{ "TLB Modified Exception", 0x0180 };
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{ "Breakpoint", 0x180, ExcCodeBp };
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template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
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{ "DSP Disabled Fault", 0x001a };
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{ "DSP Disabled Fault", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<MachineCheckFault>::vals =
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{ "Machine Check", 0x180, ExcCodeMCheck };
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template <> FaultVals MipsFault<ResetFault>::vals =
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{ "Reset Fault", 0x000, ExcCodeDummy };
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template <> FaultVals MipsFault<SoftResetFault>::vals =
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{ "Soft Reset Fault", 0x000, ExcCodeDummy };
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template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
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{ "Non Maskable Interrupt", 0x000, ExcCodeDummy };
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template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
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{ "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
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template <> FaultVals MipsFault<InterruptFault>::vals =
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{ "Interrupt", 0x000, ExcCodeInt };
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template <> FaultVals MipsFault<AddressErrorFault>::vals =
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{ "Address Error", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<TlbInvalidFault>::vals =
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{ "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<TlbRefillFault>::vals =
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{ "TLB Refill Exception", 0x180, ExcCodeDummy };
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template <> FaultVals MipsFault<TlbModifiedFault>::vals =
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{ "TLB Modified Exception", 0x180, ExcCodeMod };
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void
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MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
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@ -129,118 +131,28 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
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tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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}
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#if FULL_SYSTEM
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void
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IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xC);
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// Set new PC
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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if (!status.bev) {
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// See MIPS ARM Vol 3, Revision 2, Page 38
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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if (FULL_SYSTEM) {
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DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
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setExceptionState(tc, code());
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tc->pcState(vect(tc));
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} else {
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tc->pcState(0xBFC00200);
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panic("Fault %s encountered.\n", name());
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}
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}
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void
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TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xD);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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}
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void
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BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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setExceptionState(tc, 0x9);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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}
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void
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AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, store ? 0x5 : 0x4);
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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}
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void
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TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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setTlbExceptionState(tc, store ? 0x3 : 0x2);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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}
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void
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TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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// Since handler depends on EXL bit, must check EXL bit before setting it!!
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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setTlbExceptionState(tc, store ? 0x3 : 0x2);
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// See MIPS ARM Vol 3, Revision 2, Page 38
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if (status.exl == 1) {
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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} else {
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tc->pcState(tc->readMiscReg(MISCREG_EBASE));
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}
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}
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void
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TlbModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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setTlbExceptionState(tc, 0x1);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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}
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void
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SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x8);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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}
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void
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InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x0A);
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CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
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if (cause.iv) {
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// Offset 200 for release 2
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tc->pcState(0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
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} else {
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//Ofset at 180 for release 1
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tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
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}
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}
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#endif // FULL_SYSTEM
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void
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ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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/* All reset activity must be invoked from here */
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tc->pcState(vect());
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DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
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#endif
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if (FULL_SYSTEM) {
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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/* All reset activity must be invoked from here */
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Addr handler = vect(tc);
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tc->pcState(handler);
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DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
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}
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// Set Coprocessor 1 (Floating Point) To Usable
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StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
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@ -249,46 +161,15 @@ ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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}
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void
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ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0x0A);
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tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
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#else
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panic("%s encountered.\n", name());
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#endif
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panic("Soft reset not implemented.\n");
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}
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void
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ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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panic("%s encountered.\n", name());
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}
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void
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DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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panic("%s encountered.\n", name());
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}
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void
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CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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#if FULL_SYSTEM
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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setExceptionState(tc, 0xb);
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// The ID of the coprocessor causing the exception is stored in
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// CoprocessorUnusableFault::coProcID
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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cause.ce = coProcID;
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tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
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tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
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#else
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warn("%s (CP%d) encountered.\n", name(), coProcID);
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#endif
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panic("Non maskable interrupt not implemented.\n");
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}
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} // namespace MipsISA
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@ -44,21 +44,63 @@ namespace MipsISA
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typedef const Addr FaultVect;
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enum ExcCode {
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// A dummy value to use when the code isn't defined or doesn't matter.
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ExcCodeDummy = 0,
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ExcCodeInt = 0,
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ExcCodeMod = 1,
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ExcCodeTlbL = 2,
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ExcCodeTlbS = 3,
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ExcCodeAdEL = 4,
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ExcCodeAdES = 5,
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ExcCodeIBE = 6,
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ExcCodeDBE = 7,
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ExcCodeSys = 8,
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ExcCodeBp = 9,
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ExcCodeRI = 10,
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ExcCodeCpU = 11,
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ExcCodeOv = 12,
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ExcCodeTr = 13,
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ExcCodeC2E = 18,
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ExcCodeMDMX = 22,
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ExcCodeWatch = 23,
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ExcCodeMCheck = 24,
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ExcCodeThread = 25,
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ExcCodeCacheErr = 30
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};
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class MipsFaultBase : public FaultBase
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{
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public:
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struct FaultVals
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{
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const FaultName name;
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const FaultVect vect;
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const FaultVect offset;
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const ExcCode code;
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};
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{}
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#endif
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void setExceptionState(ThreadContext *, uint8_t);
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virtual FaultVect offset(ThreadContext *tc) const = 0;
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virtual ExcCode code() const = 0;
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virtual FaultVect base(ThreadContext *tc) const
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{
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StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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if (status.bev)
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return tc->readMiscReg(MISCREG_EBASE);
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else
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return 0xbfc00200;
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}
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FaultVect
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vect(ThreadContext *tc) const
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{
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return base(tc) + offset(tc);
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}
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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template <typename T>
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@ -68,7 +110,81 @@ class MipsFault : public MipsFaultBase
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static FaultVals vals;
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public:
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FaultName name() const { return vals.name; }
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FaultVect vect() const { return vals.vect; }
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FaultVect offset(ThreadContext *tc) const { return vals.offset; }
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ExcCode code() const { return vals.code; }
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};
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class SystemCallFault : public MipsFault<SystemCallFault> {};
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class ReservedInstructionFault : public MipsFault<ReservedInstructionFault> {};
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class ThreadFault : public MipsFault<ThreadFault> {};
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class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {};
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class TrapFault : public MipsFault<TrapFault> {};
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class BreakpointFault : public MipsFault<BreakpointFault> {};
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class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> {};
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class MachineCheckFault : public MipsFault<MachineCheckFault>
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{
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public:
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bool isMachineCheckFault() { return true; }
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};
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static inline Fault genMachineCheckFault()
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{
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return new MachineCheckFault;
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}
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class ResetFault : public MipsFault<ResetFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class SoftResetFault : public MipsFault<SoftResetFault>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
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{
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public:
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
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{
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protected:
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int coProcID;
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public:
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CoprocessorUnusableFault(int _procid) : coProcID(_procid)
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{}
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void
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invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{
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MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
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if (FULL_SYSTEM) {
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CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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cause.ce = coProcID;
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tc->setMiscReg(MISCREG_CAUSE, cause);
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}
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}
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};
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class InterruptFault : public MipsFault<InterruptFault>
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{
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public:
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FaultVect
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offset(ThreadContext *tc) const
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{
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CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
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return cause.iv ? 0x200 : 0x000;
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}
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};
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template <typename T>
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@ -80,6 +196,30 @@ class AddressFault : public MipsFault<T>
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AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
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{}
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void
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invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr)
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{
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MipsFault<T>::invoke(tc, inst);
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if (FULL_SYSTEM)
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
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}
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};
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class AddressErrorFault : public AddressFault<AddressErrorFault>
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{
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public:
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AddressErrorFault(Addr _vaddr, bool _store) :
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AddressFault<AddressErrorFault>(_vaddr, _store)
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{}
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ExcCode
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code() const
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{
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return store ? ExcCodeAdES : ExcCodeAdEL;
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}
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};
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template <typename T>
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@ -96,7 +236,6 @@ class TlbFault : public AddressFault<T>
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void
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setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
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{
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DPRINTF(MipsPRA, "%s encountered.\n", name());
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this->setExceptionState(tc, excCode);
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tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
|
||||
|
|
@ -110,122 +249,25 @@ class TlbFault : public AddressFault<T>
|
|||
context.badVPN2 = this->vpn >> 2;
|
||||
tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
|
||||
}
|
||||
};
|
||||
|
||||
class MachineCheckFault : public MipsFault<MachineCheckFault>
|
||||
{
|
||||
public:
|
||||
bool isMachineCheckFault() {return true;}
|
||||
};
|
||||
void
|
||||
invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
|
||||
{
|
||||
if (FULL_SYSTEM) {
|
||||
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
|
||||
tc->pcState(this->vect(tc));
|
||||
setTlbExceptionState(tc, this->code());
|
||||
} else {
|
||||
AddressFault<T>::invoke(tc, inst);
|
||||
}
|
||||
}
|
||||
|
||||
static inline Fault genMachineCheckFault()
|
||||
{
|
||||
return new MachineCheckFault;
|
||||
}
|
||||
|
||||
class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
|
||||
{
|
||||
public:
|
||||
bool isNonMaskableInterrupt() {return true;}
|
||||
};
|
||||
|
||||
class AddressErrorFault : public AddressFault<AddressErrorFault>
|
||||
{
|
||||
public:
|
||||
AddressErrorFault(Addr _vaddr, bool _store) :
|
||||
AddressFault<AddressErrorFault>(_vaddr, _store)
|
||||
{}
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
class ResetFault : public MipsFault<ResetFault>
|
||||
{
|
||||
public:
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
|
||||
};
|
||||
|
||||
class SystemCallFault : public MipsFault<SystemCallFault>
|
||||
{
|
||||
public:
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
};
|
||||
|
||||
class SoftResetFault : public MipsFault<SoftResetFault>
|
||||
{
|
||||
public:
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
};
|
||||
|
||||
class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
|
||||
{
|
||||
protected:
|
||||
int coProcID;
|
||||
public:
|
||||
CoprocessorUnusableFault(int _procid) : coProcID(_procid)
|
||||
{}
|
||||
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
};
|
||||
|
||||
class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
|
||||
{
|
||||
public:
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
};
|
||||
|
||||
class ThreadFault : public MipsFault<ThreadFault>
|
||||
{
|
||||
public:
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
};
|
||||
|
||||
class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
|
||||
{
|
||||
public:
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
};
|
||||
|
||||
class InterruptFault : public MipsFault<InterruptFault>
|
||||
{
|
||||
public:
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
};
|
||||
|
||||
class TrapFault : public MipsFault<TrapFault>
|
||||
{
|
||||
public:
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
};
|
||||
|
||||
class BreakpointFault : public MipsFault<BreakpointFault>
|
||||
{
|
||||
public:
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
ExcCode
|
||||
code() const
|
||||
{
|
||||
return this->store ? ExcCodeTlbS : ExcCodeTlbL;
|
||||
}
|
||||
};
|
||||
|
||||
class TlbRefillFault : public TlbFault<TlbRefillFault>
|
||||
|
|
@ -234,10 +276,13 @@ class TlbRefillFault : public TlbFault<TlbRefillFault>
|
|||
TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
|
||||
TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
|
||||
{}
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
|
||||
FaultVect
|
||||
offset(ThreadContext *tc) const
|
||||
{
|
||||
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
|
||||
return status.exl ? 0x180 : 0x000;
|
||||
}
|
||||
};
|
||||
|
||||
class TlbInvalidFault : public TlbFault<TlbInvalidFault>
|
||||
|
|
@ -246,10 +291,6 @@ class TlbInvalidFault : public TlbFault<TlbInvalidFault>
|
|||
TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
|
||||
TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
|
||||
{}
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
};
|
||||
|
||||
class TlbModifiedFault : public TlbFault<TlbModifiedFault>
|
||||
|
|
@ -258,17 +299,8 @@ class TlbModifiedFault : public TlbFault<TlbModifiedFault>
|
|||
TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
|
||||
TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
|
||||
{}
|
||||
#if FULL_SYSTEM
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
#endif
|
||||
};
|
||||
|
||||
class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
|
||||
{
|
||||
public:
|
||||
void invoke(ThreadContext * tc,
|
||||
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
|
||||
ExcCode code() const { return vals.code; }
|
||||
};
|
||||
|
||||
} // namespace MipsISA
|
||||
|
|
|
|||
Loading…
Reference in a new issue