Andreas Hansson 1031b824b9 MEM: Move port creation to the memory object(s) construction ... This patch moves all port creation from the getPort method to be consistently done in the MemObject's constructor. This is possible thanks to the Swig interface passing the length of the vector ports. Previously there was a mix of: 1) creating the ports as members (at object construction time) and using getPort for the name resolution, or 2) dynamically creating the ports in the getPort call. This is now uniform. Furthermore, objects that would not be complete without a port have these ports as members rather than having pointers to dynamically allocated ports. This patch also enables an elaboration-time enumeration of all the ports in the system which can be used to determine the masterId.		2012-02-24 11:43:53 -05:00
..
arch	MEM: Move port creation to the memory object(s) construction	2012-02-24 11:43:53 -05:00
base	Merge with head, hopefully the last time for this batch.	2012-01-31 22:40:08 -08:00
cpu	MEM: Move port creation to the memory object(s) construction	2012-02-24 11:43:53 -05:00
dev	MEM: Move port creation to the memory object(s) construction	2012-02-24 11:43:53 -05:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	CPU: Round-two unifying instr/data CPU ports across models	2012-02-24 11:42:00 -05:00
mem	MEM: Move port creation to the memory object(s) construction	2012-02-24 11:43:53 -05:00
python	SimObject: make get_config_as_dict() tolerate undefined params	2012-02-20 08:11:14 -08:00
sim	MEM: Introduce the master/slave port roles in the Python classes	2012-02-13 06:43:09 -05:00
unittest	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	clang: Enable compiling gem5 using clang 2.9 and 3.0	2012-01-31 12:05:52 -05:00