Andreas Hansson 1031b824b9 MEM: Move port creation to the memory object(s) construction ... This patch moves all port creation from the getPort method to be consistently done in the MemObject's constructor. This is possible thanks to the Swig interface passing the length of the vector ports. Previously there was a mix of: 1) creating the ports as members (at object construction time) and using getPort for the name resolution, or 2) dynamically creating the ports in the getPort call. This is now uniform. Furthermore, objects that would not be complete without a port have these ports as members rather than having pointers to dynamically allocated ports. This patch also enables an elaboration-time enumeration of all the ports in the system which can be used to determine the masterId.		2012-02-24 11:43:53 -05:00
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alpha	Merge with head, hopefully the last time for this batch.	2012-01-31 22:40:08 -08:00
arm	MEM: Move port creation to the memory object(s) construction	2012-02-24 11:43:53 -05:00
generic	clang: Enable compiling gem5 using clang 2.9 and 3.0	2012-01-31 12:05:52 -05:00
mips	Merge with head, hopefully the last time for this batch.	2012-01-31 22:40:08 -08:00
noisa	cpu: add separate stats for insts/ops both globally and per cpu model	2012-02-12 16:07:39 -06:00
power	Merge with main repository.	2012-01-30 21:07:57 -08:00
sparc	SPARC: Make PSTATE and HPSTATE a BitUnion.	2012-02-11 14:16:38 -08:00
x86	MEM: Move port creation to the memory object(s) construction	2012-02-24 11:43:53 -05:00
isa_parser.py	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	2011-09-26 23:48:54 -07:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	Faults: Turn off arch/faults.hh	2012-02-07 04:43:21 -08:00