ARM: update TLB to set request packet ASID field

This commit is contained in:
Daniel Johnson 2011-09-13 12:06:13 -05:00
parent 52d30813ca
commit cbb23a1d3c
3 changed files with 8 additions and 1 deletions

View file

@ -436,6 +436,11 @@ namespace ArmISA
Bitfield<31,30> or7;
EndBitUnion(NMRR)
BitUnion32(CONTEXTIDR)
Bitfield<7,0> asid;
Bitfield<31,8> procid;
EndBitUnion(CONTEXTIDR)
BitUnion32(L2CTLR)
Bitfield<2,0> sataRAMLatency;
Bitfield<4,3> reserved_4_3;

View file

@ -467,6 +467,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
bool is_write = (mode == Write);
bool is_priv = isPriv && !(flags & UserMode);
req->setAsid(contextId.asid);
DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
isPriv, flags & UserMode);
// If this is a clrex instruction, provide a PA of 0 with no fault

View file

@ -222,7 +222,7 @@ class TLB : public BaseTLB
protected:
SCTLR sctlr;
bool isPriv;
uint32_t contextId;
CONTEXTIDR contextId;
PRRR prrr;
NMRR nmrr;
uint32_t dacr;