sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Get rid of more uses of FULL_SYSTEM.

Browse source
This commit is contained in:
Gabe Black 2011-10-30 00:33:02 -07:00
parent facb40f3ff
commit 1d8822a364
10 changed files with 22 additions and 82 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
src/arch/x86/bios/SConscript
View file

@ -40,20 +40,19 @@
Import('*')
if env['TARGET_ISA'] == 'x86':
if env['FULL_SYSTEM']:
# The table generated by the bootloader using the BIOS and passed to
# the operating system which maps out physical memory.
SimObject('E820.py')
Source('e820.cc')
# The table generated by the bootloader using the BIOS and passed to
# the operating system which maps out physical memory.
SimObject('E820.py')
Source('e820.cc')
# The DMI tables.
SimObject('SMBios.py')
Source('smbios.cc')
# The DMI tables.
SimObject('SMBios.py')
Source('smbios.cc')
# Intel Multiprocessor Specification Configuration Table
SimObject('IntelMP.py')
Source('intelmp.cc')
# Intel Multiprocessor Specification Configuration Table
SimObject('IntelMP.py')
Source('intelmp.cc')
# ACPI system description tables
SimObject('ACPI.py')
Source('acpi.cc')
# ACPI system description tables
SimObject('ACPI.py')
Source('acpi.cc')

1
src/arch/x86/interrupts.cc
View file

@ -40,6 +40,7 @@
#include "arch/x86/regs/apic.hh"
#include "arch/x86/interrupts.hh"
#include "arch/x86/intmessage.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "debug/LocalApic.hh"
#include "dev/x86/i82094aa.hh"

1
src/arch/x86/interrupts.hh
View file

@ -44,7 +44,6 @@
#include "arch/x86/faults.hh"
#include "arch/x86/intmessage.hh"
#include "base/bitfield.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "dev/x86/intdev.hh"
#include "dev/io_device.hh"

9
src/arch/x86/mmapped_ipr.hh
View file

@ -47,7 +47,6 @@
*/
#include "arch/x86/regs/misc.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
@ -57,25 +56,18 @@ namespace X86ISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
#if !FULL_SYSTEM
panic("Shouldn't have a memory mapped register in SE\n");
#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data = htog(xc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->setData(((uint8_t *)&data) + offset);
#endif
return xc->getCpuPtr()->ticks(1);
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
#if !FULL_SYSTEM
panic("Shouldn't have a memory mapped register in SE\n");
#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data;
@ -84,7 +76,6 @@ namespace X86ISA
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->writeData(((uint8_t *)&data) + offset);
xc->setMiscReg(index, gtoh(data));
#endif
return xc->getCpuPtr()->ticks(1);
}
};

1
src/arch/x86/remote_gdb.cc
View file

@ -47,7 +47,6 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
using namespace std;

17
src/arch/x86/tlb.cc
View file

@ -49,7 +49,6 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
@ -406,28 +405,12 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(fault, req, tc, mode);
}
#if FULL_SYSTEM
Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
return tc->getCpuPtr()->ticks(1);
}
Tick
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
return tc->getCpuPtr()->ticks(1);
}
Walker *
TLB::getWalker()
{
return walker;
}
#endif
void
TLB::serialize(std::ostream &os)
{

6
src/arch/x86/tlb.hh
View file

@ -46,7 +46,6 @@
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
#include "config/full_system.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
@ -116,11 +115,6 @@ namespace X86ISA
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
#endif
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing

17
src/arch/x86/utility.cc
View file

@ -38,11 +38,7 @@
* Authors: Gabe Black
*/
#include "config/full_system.hh"
#if FULL_SYSTEM
#include "arch/x86/interrupts.hh"
#endif
#include "arch/x86/registers.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/utility.hh"
@ -55,15 +51,10 @@ namespace X86ISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
#if FULL_SYSTEM
panic("getArgument() not implemented for x86!\n");
#else
panic("getArgument() only implemented for FULL_SYSTEM\n");
M5_DUMMY_RETURN
#endif
}
# if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
@ -193,12 +184,9 @@ void initCPU(ThreadContext *tc, int cpuId)
tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
}
#endif
void startupCPU(ThreadContext *tc, int cpuId)
{
#if FULL_SYSTEM
if (cpuId == 0) {
if (cpuId == 0 || !FullSystem) {
tc->activate(0);
} else {
// This is an application processor (AP). It should be initialized to
@ -206,9 +194,6 @@ void startupCPU(ThreadContext *tc, int cpuId)
// a halted state.
tc->suspend(0);
}
#else
tc->activate(0);
#endif
}
void

18
src/arch/x86/utility.hh
View file

@ -45,9 +45,9 @@
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
class ThreadContext;
@ -68,12 +68,12 @@ namespace X86ISA
static inline bool
inUserMode(ThreadContext *tc)
{
#if FULL_SYSTEM
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
return m5reg.cpl == 3;
#else
return true;
#endif
if (!FullSystem) {
return true;
} else {
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
return m5reg.cpl == 3;
}
}
/**
@ -83,12 +83,8 @@ namespace X86ISA
template <class TC>
void zeroRegisters(TC *tc);
#if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId);
#endif
void startupCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);

7
src/arch/x86/vtophys.cc
View file

@ -43,7 +43,6 @@
#include "arch/x86/tlb.hh"
#include "arch/x86/vtophys.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "sim/fault_fwd.hh"
@ -55,16 +54,12 @@ namespace X86ISA
Addr
vtophys(Addr vaddr)
{
#if FULL_SYSTEM
panic("Need access to page tables\n");
#endif
return vaddr;
}
Addr
vtophys(ThreadContext *tc, Addr vaddr)
{
#if FULL_SYSTEM
Walker *walker = tc->getDTBPtr()->getWalker();
Addr size;
Addr addr = vaddr;
@ -75,7 +70,5 @@ namespace X86ISA
Addr paddr = addr | masked_addr;
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
#endif
return vaddr;
}
}