Andreas Hansson cfc268ad9e MEM: Make the RubyPort physMemPort a PioPort instead of M5Port ... This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system.		2012-01-30 05:38:24 -05:00
..
arch	MEM: Clean-up of Functional/Virtual/TranslatingPort remnants	2012-01-30 03:44:25 -05:00
base	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
cpu	MEM: Clean-up of Functional/Virtual/TranslatingPort remnants	2012-01-30 03:44:25 -05:00
dev	ns_gige: Fix a missing curly brace in if-statement	2012-01-27 12:54:11 -05:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	MEM: Clean-up of Functional/Virtual/TranslatingPort remnants	2012-01-30 03:44:25 -05:00
mem	MEM: Make the RubyPort physMemPort a PioPort instead of M5Port	2012-01-30 05:38:24 -05:00
python	MEM: Removing the default port peer from Python ports	2012-01-17 12:55:09 -06:00
sim	sim: display final value of curTick in stats	2012-01-25 17:18:25 +00:00
unittest	Stats: Add a sparse histogram stat object.	2011-08-19 15:08:05 -05:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	SWIG: Make gem5 compile and link with swig 2.0.4	2012-01-09 18:08:20 -06:00