MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
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6 changed files with 42 additions and 33 deletions
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@ -147,11 +147,16 @@ def make_level(spec, prototypes, attach_obj, attach_port):
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fanout = spec[0]
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parent = attach_obj # use attach obj as config parent too
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if len(spec) > 1 and (fanout > 1 or options.force_bus):
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port = getattr(attach_obj, attach_port)
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new_bus = Bus(clock="500MHz", width=16)
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new_bus.port = getattr(attach_obj, attach_port)
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if (port.role == 'MASTER'):
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new_bus.slave = port
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attach_port = "master"
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else:
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new_bus.master = port
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attach_port = "slave"
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parent.cpu_side_bus = new_bus
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attach_obj = new_bus
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attach_port = "port"
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objs = [prototypes[0]() for i in xrange(fanout)]
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if len(spec) > 1:
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# we just built caches, more levels to go
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@ -178,6 +183,10 @@ if options.atomic:
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else:
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root.system.mem_mode = 'timing'
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# The system port is never used in the tester so merely connect it
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# to avoid problems
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root.system.system_port = root.system.physmem.port
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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@ -221,19 +221,19 @@ system.l2 = L2(size = options.l2size, assoc = 8)
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# Connect the L2 cache and memory together
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# ----------------------
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system.physmem.port = system.membus.port
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system.l2.cpu_side = system.toL2bus.port
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system.l2.mem_side = system.membus.port
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system.physmem.port = system.membus.master
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system.l2.cpu_side = system.toL2bus.slave
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system.l2.mem_side = system.membus.master
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# ----------------------
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# Connect the L2 cache and clusters together
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# ----------------------
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for cluster in clusters:
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cluster.l1.cpu_side = cluster.clusterbus.port
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cluster.l1.mem_side = system.toL2bus.port
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cluster.l1.cpu_side = cluster.clusterbus.master
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cluster.l1.mem_side = system.toL2bus.slave
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for cpu in cluster.cpus:
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cpu.icache_port = cluster.clusterbus.port
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cpu.dcache_port = cluster.clusterbus.port
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cpu.icache_port = cluster.clusterbus.slave
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cpu.dcache_port = cluster.clusterbus.slave
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# ----------------------
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# Define the root
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@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
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# Connect the L2 cache and memory together
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# ----------------------
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system.physmem.port = system.membus.port
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system.l2.cpu_side = system.toL2bus.port
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system.l2.mem_side = system.membus.port
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system.system_port = system.membus.port
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system.physmem.port = system.membus.master
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system.l2.cpu_side = system.toL2bus.master
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system.l2.mem_side = system.membus.slave
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system.system_port = system.membus.slave
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# ----------------------
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# Connect the L2 cache and clusters together
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@ -376,7 +376,7 @@ class VExpress_ELT(RealView):
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self.elba_kmi1.pio = bus.master
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self.cf_ctrl.pio = bus.master
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self.cf_ctrl.config = bus.master
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self.cf_ctrl.dma = bus.port
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self.cf_ctrl.dma = bus.slave
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self.ide.pio = bus.master
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self.ide.config = bus.master
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self.ide.dma = bus.slave
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@ -63,6 +63,6 @@ class Malta(Platform):
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.cchip.pio = bus.port
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self.io.pio = bus.port
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self.uart.pio = bus.port
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self.cchip.pio = bus.master
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self.io.pio = bus.master
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self.uart.pio = bus.master
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@ -109,8 +109,8 @@ class T1000(Platform):
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iob = Iob()
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# Attach I/O devices that are on chip
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def attachOnChipIO(self, bus):
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self.iob.pio = bus.port
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self.htod.pio = bus.port
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self.iob.pio = bus.master
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self.htod.pio = bus.master
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# Attach I/O devices to specified bus object. Can't do this
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@ -119,17 +119,17 @@ class T1000(Platform):
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def attachIO(self, bus):
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self.hvuart.terminal = self.hterm
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self.puart0.terminal = self.pterm
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self.fake_clk.pio = bus.port
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self.fake_membnks.pio = bus.port
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self.fake_l2_1.pio = bus.port
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self.fake_l2_2.pio = bus.port
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self.fake_l2_3.pio = bus.port
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self.fake_l2_4.pio = bus.port
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self.fake_l2esr_1.pio = bus.port
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self.fake_l2esr_2.pio = bus.port
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self.fake_l2esr_3.pio = bus.port
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self.fake_l2esr_4.pio = bus.port
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self.fake_ssi.pio = bus.port
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self.fake_jbi.pio = bus.port
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self.puart0.pio = bus.port
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self.hvuart.pio = bus.port
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self.fake_clk.pio = bus.master
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self.fake_membnks.pio = bus.master
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self.fake_l2_1.pio = bus.master
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self.fake_l2_2.pio = bus.master
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self.fake_l2_3.pio = bus.master
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self.fake_l2_4.pio = bus.master
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self.fake_l2esr_1.pio = bus.master
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self.fake_l2esr_2.pio = bus.master
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self.fake_l2esr_3.pio = bus.master
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self.fake_l2esr_4.pio = bus.master
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self.fake_ssi.pio = bus.master
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self.fake_jbi.pio = bus.master
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self.puart0.pio = bus.master
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self.hvuart.pio = bus.master
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