Commit graph

2706 commits

Author SHA1 Message Date
William Wang
f9d403a7b9 MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 09:40:11 -04:00
Andreas Hansson
312efd742e Power: Change bitfield name to avoid conflicts with range_map
This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.
2012-03-26 05:35:24 -04:00
Nathanael Premillieu
8e2a8fbb7e ARM: Fix case where cond/uncond control is mis-specified 2012-03-21 10:34:06 -05:00
Ali Saidi
ed8ed6e761 ARM: Clean up condCodes in IT blocks. 2012-03-21 10:34:06 -05:00
Geoffrey Blake
a64319f764 ARM: IT doesn't need to be serializing. 2012-03-21 10:34:06 -05:00
Andreas Hansson
72538294fb gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
2012-03-19 06:36:09 -04:00
Andreas Hansson
adb8621031 clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
2012-03-19 06:35:04 -04:00
Brian Grayson
9a9a4a0780 ARM: Fix branch prediction issue with CB(N)Z instruction 2012-03-09 15:32:41 -05:00
Geoffrey Blake
98cf57fb89 CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.
2012-03-09 09:59:28 -05:00
Geoffrey Blake
043709fdfa CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.
2012-03-09 09:59:27 -05:00
Ali Saidi
df05ffab12 ARM: Don't reset CPUs that are going to be switched in. 2012-03-09 09:59:26 -05:00
Ali Saidi
3ce2d0fad0 System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
2012-03-09 09:59:26 -05:00
Ali Saidi
ec1ef24895 ARM: Fix valgrind reported error on O3 that was causing minor stats changes. 2012-03-09 09:59:26 -05:00
Ali Saidi
b129d7ce00 ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
2012-03-02 08:18:19 -06:00
Ali Saidi
91b737ed48 ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
2012-03-01 17:26:31 -06:00
Matt Horsnell
08187e3916 ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
2012-03-01 17:26:31 -06:00
Dam Sunwoo
86d1042d9f ARM: move kernel func event to correct location.
With the recent series of patches, the symbol table loading moved from
"construct" time to "init" time, but the kernel function event
callback registration was left behind. This patch moves it to the
proper location.
2012-03-01 17:26:31 -06:00
Giacomo Gabrielli
d51478db4e ARM: fix bits-to-fp conversion function declarations.
Add extra declarations to allow the compiler to pick up the right function.
Please note that these declarations have been added as part of the
clang-related changes.
2012-03-01 17:26:30 -06:00
Nilay Vaish
4b32c9fb4d x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
2012-03-01 11:37:03 -06:00
Gabe Black
559b43a372 X86: Use the M5PanicFault fault in execute methods instead of calling panic.
If an instruction is executed speculatively and hits a situation where it
wants to panic, it should return a fault instead. If the instruction was
misspeculated, the fault can be thrown away. If the instruction wasn't
misspeculated, the fault will be invoked and the panic will still happen.
2012-02-26 15:32:53 -08:00
Andreas Hansson
9e3c8de30b MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would
not be complete without a port proxy by making the proxies members
rathen than dynamically allocated. In essence, if NULL would not be a
valid value for the proxy, then we avoid using a pointer to make this
clear.

The same approach is used for the methods using these proxies, such as
loadSections, that now use references rather than pointers to better
reflect the fact that NULL would not be an acceptable value (in fact
the code would break and that is how this patch started out).

Overall the concept of "using a reference to express unconditional
composition where a NULL pointer is never valid" could be done on a
much broader scale throughout the code base, but for now it is only
done in the locations affected by the proxies.
2012-02-24 11:45:30 -05:00
Andreas Hansson
1031b824b9 MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.

This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
2012-02-24 11:43:53 -05:00
Andreas Hansson
5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Gabe Black
eada4268ef X86: open flags: Another patch from Vince Weaver 2012-02-12 16:41:29 -08:00
Anthony Gutierrez
542d0ceebc cpu: add separate stats for insts/ops both globally and per cpu model 2012-02-12 16:07:39 -06:00
Ali Saidi
8aaa39e93d mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
2012-02-12 16:07:38 -06:00
Gabe Black
5b557a314f SPARC: Make PSTATE and HPSTATE a BitUnion.
This gets rid of cryptic bits of code with lots of bit manipulation, and makes
some comments redundant.
2012-02-11 14:16:38 -08:00
Gabe Black
f2b46fdb85 Faults: Turn off arch/faults.hh
Because there are no longer architecture independent but specialized functions
in arch/XXX/faults.hh, code that isn't using the faults from a particular ISA
no longer needs to be able to include them through the switching header file
arch/faults.hh. By removing that header file (arch/faults.hh), the potential
interface between ISA code and non ISA code is narrowed.
2012-02-07 04:43:21 -08:00
Gabe Black
ea8b347dc5 Merge with head, hopefully the last time for this batch. 2012-01-31 22:40:08 -08:00
Koan-Sin Tan
7d4f187700 clang: Enable compiling gem5 using clang 2.9 and 3.0
This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.
2012-01-31 12:05:52 -05:00
Dam Sunwoo
0ed3c84c7b util: implements "writefile" gem5 op to export file from guest to host filesystem
Usage: m5 writefile <filename>

File will be created in the gem5 output folder with the identical filename.
Implementation is largely based on the existing "readfile" functionality.
Currently does not support exporting of folders.
2012-01-31 07:46:04 -08:00
Geoffrey Blake
af6aaf2581 CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU.  These changes have only been tested with the ARM ISA.  Other
ISAs potentially require modification.
2012-01-31 07:46:03 -08:00
Gabe Black
e88165a431 Merge with main repository. 2012-01-30 21:07:57 -08:00
Andreas Hansson
ef9fc01073 MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
This patch cleans up forward declarations and a member-function
prototype that still referred to the old FunctionalPort, VirtualPort
and TranslatingPort. There is no change in functionality.
2012-01-30 03:44:25 -05:00
Gabe Black
dc0e629ea1 Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
2012-01-29 02:04:34 -08:00
Gabe Black
eab5c60286 MIPS: Fix a compiler warning from the eret instruction. 2012-01-28 07:24:23 -08:00
Gabe Black
c3d41a2def Merge with the main repo.
--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-28 07:24:01 -08:00
Gabe Black
da2a4acc26 Merge yet again with the main repository. 2012-01-16 04:27:10 -08:00
Andreas Hansson
07cf9d914b MEM: Separate queries for snooping and address ranges
This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.
2012-01-17 12:55:09 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Steve Reinhardt
7a3a37307a Alpha: warn_once about broken PAL breakpoints.
A recent changeset (aae12ce9f34c) removed support for
PAL-mode breakpoints in Alpha, since it was awkward
and likely unused.  This patch lets a user know if they
potentially run into this limitation.
2012-01-16 19:01:27 -08:00
Deyuan Guo
4a59cf00b4 mips: compatibility between MIPS_SE and cross compiler from CodeSorcery 2012-01-12 09:59:01 -05:00
Deyuan Guo
31b6941a52 mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FS 2012-01-12 09:59:00 -05:00
Deyuan Guo
a40ec5671f mips: Fix decoder of two float-convert instructions 2012-01-12 09:58:59 -05:00
Deyuan Guo
7f782a6c79 mips: definition of MIPS64_QNAN in registers.hh 2012-01-12 09:58:58 -05:00
Nilay Vaish
acbc03ae46 X86: Add memory fence to I/O instructions 2012-01-09 20:13:31 -06:00
Ali Saidi
80a6907927 ARM: Add support for initparam m5 op 2012-01-09 18:08:20 -06:00
Gabe Black
241cc0c840 Another merge with the main repository. 2012-01-07 02:16:37 -08:00
Gabe Black
ec936364b7 Merge with the main repository again. 2012-01-07 02:15:35 -08:00
Gabe Black
36a822f08e Merge with main repository. 2012-01-07 02:10:34 -08:00
Nilay Vaish
bd23a37198 X86 TLB: Move a DPRINTF to its correct place
The DPRINTF for doing protection checks appears after the checks have been
carried out. It is possible that the function returns while the checks are
being carried, in which case the printf is missed out. This patch moves the
DPRINTF before the checks.

--HG--
extra : rebase_source : 172896057e593022444d882ea93323a5d9f77a89
2012-01-05 11:00:32 -06:00
Nathan Binkert
6ef9691035 gcc: fix unused variable warnings from GCC 4.6.1
--HG--
extra : rebase_source : f9e22de341493a25ac6106c16ac35c61c128a080
2011-12-13 11:49:27 -08:00
Mitchell Hayenga
fa753c1454 Device: Make changes necessary to support a coherent page walker cache.
Adds the flag 'recvSnoops' which enables pagewalkers using DmaPorts,
to properly configure snoops.

--HG--
extra : rebase_source : 64207bef62c3268ddff2236ee4adae873812325f
2011-12-01 00:15:22 -08:00
Ali Saidi
5901c5223f ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .
Squashes the subsequent instructions in O3 pipe after the service call, so that
they see the effect of the system call when re-executed. This isn't really an issue
with FS mode, but can show up in SE mode.

--HG--
extra : rebase_source : 613a69fe1d9834261e25a8cd340aa6b47578e1fe
2011-12-01 00:15:22 -08:00
Gabe Black
93fb460fad X86: Fix a bad segmentation check for the stack segment.
--HG--
extra : rebase_source : 755f4f6eae52f88ed516a1f1ac9e2565725d89c1
2011-12-01 00:17:14 -05:00
Gabe Black
87b66c9ae3 SPARC: Minor style fix.
I forgot to fix this as well per Ali's feedback.

--HG--
extra : rebase_source : e70d031cb5f91e2212a1a73ea1769bf0549b826c
2011-11-28 04:35:55 -05:00
Gabe Black
e7d0c999a1 SPARC: Isolate FP operations enough to prevent code/rounding mode reordering.
--HG--
extra : rebase_source : ee79ab89c5a707c1294f38abb84c60f8ef64196c
2011-11-27 22:00:58 -05:00
Gabe Black
49a2d54e1a X86: Fix the constant detecting three byte opcodes in the predecoder.
--HG--
extra : rebase_source : b64c3d2348cb73177024695fb6e205d51bf1cda9
2011-11-20 05:10:05 -08:00
Gabe Black
85424bef19 SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
Gabe Black
ec32d85f9d Power: Add a stubbed out stacktrace.cc 2011-11-13 12:40:15 -08:00
Gabe Black
ff4ba82610 POWER: Add a stub implementation of initCPU. 2011-11-13 12:40:15 -08:00
Gabe Black
1a8f1809fa Power: Add a stub kernel_stats.hh. 2011-11-13 12:40:15 -08:00
Gabe Black
6d68887c87 Power: Implement a stub for getArgument. 2011-11-13 02:05:27 -08:00
Nilay Vaish
582ea4d543 x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
2011-11-03 22:52:21 -05:00
Gabe Black
239b33e016 SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
Gabe Black
7b417d4188 SE/FS: Get rid of the last use of FULL_SYSTEM in x86. 2011-11-01 04:01:15 -07:00
Gabe Black
b6da5e2086 SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. 2011-11-01 04:01:14 -07:00
Gabe Black
eeb85a8575 SE/FS: Remove the last uses of FULL_SYSTEM from SPARC. 2011-10-31 02:58:24 -07:00
Gabe Black
8ad2b8c559 SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
Gabe Black
d735abe5da GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
2011-10-31 01:09:44 -07:00
Gabe Black
248033f31e SE/FS: Get rid of FULL_SYSTEM in MIPS. 2011-10-30 18:39:38 -07:00
Gabe Black
37a437893e System: Push boot_cpu_frequency down into the subclasses that actually use it.
This parameter depends on a number of coincidences to work properly. First,
there must be an array assigned to system called "cpu" even though there's no
parameter called that. Second, the items in the "cpu" array have to have a
"clock" parameter which has a "frequency" member. This is true of the normal
CPUs, but isn't true of the memory tester CPUs. This happened to work before
because the memory tester CPUs were only used in SE mode where this parameter
was being excluded. Since everything is being pulled into a common binary,
this won't work any more. Since the boot_cpu_frequency parameter is only used
by Alpha's Linux System object (and Mips's through copy and paste), the
definition of that parameter is moved down to those objects specifically.
2011-10-30 17:38:09 -07:00
Gabe Black
b144f05b53 SE/FS: Remove the last references to FULL_SYSTEM from POWER. 2011-10-30 03:55:24 -07:00
Gabe Black
6dc3cedc4e X86: Build the same files in SE and FS. 2011-10-30 03:06:40 -07:00
Gabe Black
1d8822a364 X86: Get rid of more uses of FULL_SYSTEM. 2011-10-30 00:33:02 -07:00
Gabe Black
facb40f3ff SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. 2011-10-30 00:33:02 -07:00
Steve Reinhardt
6f9d294e86 SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back
through the Process to allocate memory, but did not have
a method to map addresses without allocating new pages.
It makes more sense for Process to do the allocation, so
this method was renamed allocateMem() and moved to Process,
and uses a new map() call on PageTable.

The remaining uses of the process pointer in PageTable
were only to get the name and the PID, so by passing these
in directly in the constructor, we can make PageTable
completely independent of Process.
2011-10-22 22:30:08 -07:00
Steve Reinhardt
4d5f2c28a8 syscall_emul: implement MAP_FIXED option to mmap() 2011-10-22 22:30:07 -07:00
Gabe Black
bcf664e5f9 SE/FS: Turn on the page table class in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
79ba4b6595 SPARC: Build vtophys into SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
5ee3f586bf Power: Add a stub implementation for vtophys in SE and FS. 2011-10-16 05:06:39 -07:00
Gabe Black
baae510b56 MIPS: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
1eb459a79e ARM: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
b2af015b97 ARM: Turn on the page table walker on ARM in SE mode. 2011-10-16 05:06:38 -07:00
Gabe Black
dd8fed7387 Alpha: Turn on vtophys in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
85ca77d114 X86: Build vtophys in SE mode. 2011-10-13 02:26:21 -07:00
Gabe Black
8adc6781bf X86: Turn on the page table walker in SE mode. 2011-10-13 02:22:23 -07:00
Gabe Black
4b2e5ebead SPARC: Remove the last checks of FULL_SYSTEM. 2011-10-13 01:37:19 -07:00
Gabe Black
6b5ede5e39 SPARC: Narrow the scope of #if FULL_SYSTEM in SPARC's faults. 2011-10-13 01:11:00 -07:00
Gabe Black
afa7a34563 SPARC: Let the TLB have friends in FS mode. 2011-10-10 00:38:57 -07:00
Gabe Black
8eec565d0d SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC. 2011-10-10 00:31:51 -07:00
Gabe Black
5bab52d56d [mq]: sefssparcregfile.patch 2011-10-09 23:48:27 -07:00
Gabe Black
48b40cff65 Interrupts: Make the IO APIC go get the local APICs.
This is so they don't have to declare themselves to the IO APIC and don't have
to have a pointer to the platform object.
2011-10-09 04:44:02 -07:00
Gabe Black
f338d60930 SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
Gabe Black
d368344092 SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
2011-10-04 02:26:03 -07:00
Gabe Black
e2dbe59f5d SE/FS: Remove System::platform and Platform::intrFrequency.
In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.

This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.

After this change, a platform will need to have a system, but a system won't
have to have a platform.
2011-09-30 00:29:07 -07:00
Gabe Black
91dd72a99a X86: Remove FULL_SYSTEM from the x86 faults. 2011-09-30 00:28:40 -07:00
Gabe Black
51f7a66660 SE/FS: Build the devices in SE mode. 2011-09-30 00:28:33 -07:00
Gabe Black
35e20c7470 SE/FS: Use the new FullSystem constant where possible. 2011-09-30 00:27:16 -07:00
Gabe Black
44ed4849d4 Faults: Replace calls to genMachineCheckFault with M5PanicFault. 2011-09-27 00:24:43 -07:00
Gabe Black
2ed3eef9b0 Faults: Add in generic faults that work like panics, warns, etc.
These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
2011-09-27 00:17:09 -07:00
Gabe Black
997cbe1c09 ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
2011-09-26 23:48:54 -07:00
Gabe Black
7770239792 SCons: Add a comment I forgot to add in earlier.
This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
2011-09-24 17:03:18 -07:00
Gabe Black
9f26aaa7d7 SCons: Make the ISA parser a source for its output files like the comments say.
There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
2011-09-24 16:59:11 -07:00
Gabe Black
40b6c9cb2e X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
2011-09-23 02:42:22 -07:00
Gabe Black
9a38dc6194 MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and adds
names for the exception code constants.
2011-09-19 06:17:21 -07:00
Gabe Black
4455fc484d MIPS, faults: Update how the PC is set. 2011-09-19 06:17:21 -07:00
Gabe Black
0d9ee17012 MIPS: Get rid of skipFaultInstruction and setRestartAddress.
Neither of these functions were used.
2011-09-19 06:17:21 -07:00
Gabe Black
5ea09771be MIPS: Use inheritance to consolidate class definitions. 2011-09-19 06:17:21 -07:00
Gabe Black
7d19ff170d MIPS: Always compile in setExceptionState, including in SE mode.
Also fix the newly exposed and preexisting compile errors. This code hasn't
been exposed in a while, and it's not up to date with the rest of gem5.
2011-09-19 06:17:21 -07:00
Gabe Black
48b6636d01 MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of having two
different classes. The classes were also misleadingly named since loads are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I haven't
looked at it closely.
2011-09-19 06:17:20 -07:00
Gabe Black
efcded334c MIPS: Get rid of the unused "count" field in FaultVals. 2011-09-19 06:17:20 -07:00
Gabe Black
ffeab06378 MIPS: Move the genMachineCheckFault function near MachineCheckFault.
Since they're so closely linked, they should be next to each other in the
file.
2011-09-19 06:17:20 -07:00
Gabe Black
59d7fc6b26 MIPS: Consolidate the two AddressErrorFault variants. 2011-09-19 06:17:20 -07:00
Gabe Black
717d4ae930 Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.
These functions aren't called anywhere and are probably only theoretically
useful.
2011-09-19 06:17:20 -07:00
Gabe Black
110c59b414 MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
2011-09-19 06:17:19 -07:00
Gabe Black
7e704c9f51 MIPS: Add constructors to the fault classes. 2011-09-19 06:17:19 -07:00
Gabe Black
27388c0fe0 MIPS: Use the CRTP to streamline the Fault class definitions.
CRTP stands for the curiously recurring template pattern.
2011-09-19 06:17:19 -07:00
Gabe Black
59a5605fff SPARC: Remove #if FULL_SYSTEMs from the ISA description. 2011-09-19 06:17:19 -07:00
Gabe Black
f21ae529fb MIPS: Get rid of #if style config checks in the ISA description. 2011-09-19 06:14:02 -07:00
Gabe Black
4ad36a4684 MIPS: Guard SystemCallFault::invoke consistently.
Make sure it's declared iff it's also defined.
2011-09-19 06:09:15 -07:00
Gabe Black
49967ed268 MIPS: Get rid of the unused (and partially defined) CacheError fault. 2011-09-19 05:53:54 -07:00
Gabe Black
978e41eab0 Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
2011-09-19 03:40:30 -07:00
Gabe Black
7701c5b1ec X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.
The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
2011-09-19 02:53:37 -07:00
Gabe Black
83aa47adca PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts. 2011-09-19 02:40:19 -07:00
Gabe Black
9eda6b1d88 Pseudoinst: Add an initParam pseudo inst function. 2011-09-18 23:26:39 -07:00
Daniel Johnson
cbb23a1d3c ARM: update TLB to set request packet ASID field 2011-09-13 12:06:13 -05:00
Chander Sudanthi
7c479d7349 CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13 12:06:13 -05:00
Daniel Johnson
09a6e424ec ARM: Implement numcpus bits in L2CTLR register. 2011-09-13 12:06:13 -05:00
Ali Saidi
649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
Deyuan Guo
bb921b1459 MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
2011-09-10 03:45:25 -07:00
Gabe Black
49a7ed0397 StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
2011-09-09 02:40:11 -07:00
Gabe Black
b7b545bc38 Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 02:30:01 -07:00
Gabe Black
a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
Gabe Black
f370ac5c18 ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
Gabe Black
f4dc64655f ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
2011-09-08 03:20:05 -07:00
Gabe Black
87d687e242 X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
2011-09-05 18:36:26 -07:00
Gabe Black
3bd0b9654c X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
2011-09-05 02:48:57 -07:00
Lisa Hsu
365966304e TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why.  Add a little warn() to explain it a bit.  Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-02 17:04:00 -07:00
Ali Saidi
c9d5985b82 ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
2011-08-19 15:08:08 -05:00
Ali Saidi
2fd2b44b86 ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
Ali Saidi
d2a0a2ec22 ARM: Add support for Versatile Express boards 2011-08-19 15:08:08 -05:00
Ali Saidi
b94f841969 ARM: Add support for DIV/SDIV instructions. 2011-08-19 15:08:07 -05:00
Geoffrey Blake
5f425b8bd1 Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
2011-08-19 15:08:07 -05:00
Ali Saidi
9b356adf54 ARM: Fix a memory leak with the table walker. 2011-08-19 15:08:05 -05:00
Gabe Black
1b9de61a71 X86: Use IsSquashAfter if an instruction could affect fetch translation.
Control register operands are set up so that writing to them is serialize
after, serialize before, and non-speculative. These are probably overboard,
but they should usually be safe. Unfortunately there are times when even these
aren't enough. If an instruction modifies state that affects fetch, later
serialized instructions which come after it might have already gone through
fetch and decode by the time it commits. These instructions may have been
translated incorrectly or interpretted incorrectly and need to be destroyed.
This change modifies instructions which will or may have this behavior so that
they use the IsSquashAfter flag when necessary.
2011-08-13 23:03:11 -07:00
Wade Walker
8870a5820a ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
2011-07-15 11:53:34 -05:00
Wade Walker
e6672d1f29 ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
2011-07-15 11:53:34 -05:00
Nilay Vaish
dbde1502cd X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
2011-07-11 16:52:52 -05:00
Gabe Black
a7dcd19fa0 ISA: Get rid of the unused mem_acc_type template parameter. 2011-07-11 04:47:06 -07:00
Korey Sewell
678376f0ba alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
2011-07-07 21:32:49 -04:00
Nathan Binkert
3d252f8e5f grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently.  This makes implementing an include statement as part
of a grammar possible.
2011-07-05 18:30:04 -07:00
Gabe Black
87b657278d ISAs: Streamline some spots where Mem is used in the ISA descriptions. 2011-07-05 16:52:57 -07:00
Gabe Black
63a934d152 ISA parser: Define operand types with a ctype directly. 2011-07-05 16:52:15 -07:00
Gabe Black
f16179eb21 ISA parser: Simplify operand type handling.
This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
2011-07-05 16:48:18 -07:00
Gabe Black
3a1428365a ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
2011-07-02 22:35:04 -07:00
Gabe Black
aade13769f ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
Gabe Black
2f72d6a1f4 X86: Fix store microops so they don't drop faults in timing mode.
If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.
2011-07-02 22:31:22 -07:00
Nilay Vaish
f4cfd65d29 arch: print next upc correctly
The patch corrects the print statement which prints the current and
the next pc. Instead of the next upc, the next pc was being printed.
2011-06-28 18:27:38 -05:00
Deyaun Guo
5aaddc129e mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
2011-06-22 23:35:21 -04:00
Gabe Black
efb9f7c2ae X86: Eliminate an unused argument for building store microops. 2011-06-21 19:28:14 -07:00
Korey Sewell
59686795e3 mips: mark unaligned access flag as true 2011-06-19 21:43:41 -04:00
Korey Sewell
5ef0b7a9db inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
2011-06-19 21:43:41 -04:00
Korey Sewell
83a0fd24f7 alpha: fix warn_once for prefetches 2011-06-19 21:43:40 -04:00
Korey Sewell
33a6020f2e alpha: naming for dtb faults
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
2011-06-19 21:43:40 -04:00
Korey Sewell
f268d7d004 alpha: make hwrei a control inst
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?

The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
2011-06-19 21:43:39 -04:00
Korey Sewell
d5d4e47f76 sparc: init. cache state in TLB
valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
2011-06-19 21:43:35 -04:00
Korey Sewell
b43eeaf2e2 cpus/isa: add a != operator for pcstate 2011-06-19 21:43:33 -04:00
Gedare Bloom
3f1f16703d ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 2011-06-17 12:20:10 -05:00
Ali Saidi
8b4307f8d8 ARM: Handle case where new TLB size is different from previous TLB size.
After a checkpoint we need to make sure that we restore the right
number of entries.
2011-06-16 15:08:12 -05:00
Chander Sudanthi
9fe3610b32 ARM: Fix memset on TLB flush and initialization
Instead of clearing the entire TLB on initialization and flush, the code was
clearing only one element.  This patch corrects the memsets in the init and
flush routines.
2011-06-16 15:08:11 -05:00
Korey Sewell
4229bce89d sparc: don't use directcntrl branch flag
this flag is only used for early branch resolution in the O3 model (of pc-relative branches)
but this isnt cleanly working even when the branch target code is added for sparc. For now,
we'll ignore this optimization and add a todo in the SPARC ISA for future developers
2011-06-10 22:15:32 -04:00
Korey Sewell
1a451cd2c5 sparc: compilation fixes for inorder
Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
2011-06-09 01:34:06 -04:00
Gabe Black
ab3704170e ISA parser: Loosen the regular expressions matching filenames.
The regular expressions matching filenames in the ##include directives and the
internally generated ##newfile directives where only looking for filenames
composed of alpha numeric characters, periods, and dashes. In Unix/Linux, the
rules for what characters can be in a filename are much looser than that. This
change replaces those expressions with ones that look for anything other than
a quote character. Technically quote characters are allowed as well so we
should allow escaping them somehow, but the additional complexity probably
isn't worth it.
2011-06-07 00:46:54 -07:00
Nathan Binkert
2b1aa35e20 scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
Nathan Binkert
f656787edb copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
Steve Reinhardt
8d29bda742 syscall emul: fix Power Linux mmap constant, plus other cleanup
We were getting a spurious warning in the regressions that turned
out to be due to having the wrong value for TGT_MAP_ANONYMOUS for
Power Linux, but in the process of tracking it down I ended up
doing some cleanup of the mmap handling in general.
2011-05-23 14:29:23 -07:00
Steve Reinhardt
19bb896bfe config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children.  This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration.  At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation.  For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().
2011-05-23 14:29:23 -07:00
Geoffrey Blake
6dd996aabb O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
This patch fixes two problems with the O3 cpu model. The first is an issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to issue
if the next line faults a fault is attached to a micro-op in the currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.

A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is incorrect
in the case of a macro-op as the current location might not be interruptable.
2011-05-23 10:40:18 -05:00
Nathan Binkert
22263f5091 gcc: fix an uninitialized variable warning from G++ 4.5 2011-05-18 11:06:23 -07:00
Ali Saidi
b5160ba2c3 ARM: Generate condition code setting code based on which codes are set.
This change further eliminates cases where condition codes were being read
just so they could be written without change because the instruction in
question was supposed to preserve them. This is done by creating the condition
code code based on the input rather than just doing a simple substitution.
2011-05-13 17:27:02 -05:00
Ali Saidi
05866c82f9 ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
2011-05-13 17:27:02 -05:00
Ali Saidi
401165c778 ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
2011-05-13 17:27:01 -05:00
Ali Saidi
e097c4fb18 ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
2011-05-13 17:27:01 -05:00
Ali Saidi
2178859b76 ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
2011-05-13 17:27:01 -05:00
Chander Sudanthi
4bf48a11ef Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified.  Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
2011-05-13 17:27:00 -05:00
Chander Sudanthi
5299c75e62 ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
2011-05-13 17:27:00 -05:00
Gabe Black
b8889a96b3 X86: Fix the Lldt instructions so they load the ldtr and not the tr. 2011-05-06 01:00:32 -07:00
Ali Saidi
42e7888855 ARM: Add support for loading the a bootloader and configuring parameters for it 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
1b505f5291 ARM: Implement WFE/WFI/SEV semantics. 2011-05-04 20:38:28 -05:00
Ali Saidi
ba8d64520e ARM: Add support for MP misc regs and broadcast flushes. 2011-05-04 20:38:28 -05:00
Ali Saidi
48f7fda706 ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
Ali Saidi
632cf8dd80 ARM: Fix small bug with vcvt instruction 2011-05-04 20:38:26 -05:00
Gabe Black
0554885eb9 X86: When decoding a memory only inst, fault on reg encodings, don't assert.
This change makes the decoder figure out if an instruction that only supports
memory is using a register encoding and decodes directly to "Unknown" which will
behave appropriately. This prevents other parts of the instruction creation
process from seeing the mismatch and asserting.
2011-04-23 15:02:29 -07:00
Nathan Binkert
99fbd18ea5 fix some build problems from prior changesets 2011-04-20 18:45:03 -07:00
Nathan Binkert
eddac53ff6 trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing.  This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15 10:44:32 -07:00
Nathan Binkert
f946d7bcdb debug: create a Debug namespace 2011-04-15 10:44:15 -07:00
Nathan Binkert
bbb1392c08 includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Ali Saidi
4b61abe8da ARM: Fix checkpoint restoration in ARM_SE. 2011-04-10 21:02:28 -04:00