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ARM: Better RealView/Versatile EB platform support.

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Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
This commit is contained in:
Chander Sudanthi 2011-05-13 17:27:00 -05:00
parent b79650ceaa
commit 5299c75e62
7 changed files with 43 additions and 21 deletions
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6
src/arch/arm/ArmSystem.py
View file

@ -46,6 +46,12 @@ class ArmMachineType(Enum):
class ArmSystem(System):
type = 'ArmSystem'
load_addr_mask = 0xffffffff
# 0x35 Implementor is '5' from "M5"
# 0x0 Variant
# 0xf Architecture from CPUID scheme
# 0xf00 Primary part number
# 0x0 Revision
midr_regval = Param.UInt32(0x350ff000, "MIDR value")
boot_loader = Param.String("", "File that contains the boot loader code if any")
boot_loader_mem = Param.PhysicalMemory(NULL,
"Memory object that boot loader is to be loaded into")

22
src/arch/arm/isa.cc
View file

@ -52,7 +52,7 @@ void
ISA::clear()
{
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
uint32_t midr = miscRegs[MISCREG_MIDR];
memset(miscRegs, 0, sizeof(miscRegs));
CPSR cpsr = 0;
cpsr.mode = MODE_USER;
@ -71,21 +71,12 @@ ISA::clear()
miscRegs[MISCREG_SCTLR] = sctlr;
miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
// Preserve MIDR accross reset
miscRegs[MISCREG_MIDR] = midr;
/* Start with an event in the mailbox */
miscRegs[MISCREG_SEV_MAILBOX] = 1;
/*
* Implemented = '5' from "M5",
* Variant = 0,
*/
miscRegs[MISCREG_MIDR] =
(0x35 << 24) | // Implementor is '5' from "M5"
(0 << 20) | // Variant
(0xf << 16) | // Architecture from CPUID scheme
(0xf00 << 4) | // Primary part number
(0 << 0) | // Revision
0;
// Separate Instruction and Data TLBs.
miscRegs[MISCREG_TLBTR] = 1;
@ -209,6 +200,9 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
warn("Returning thumbEE disabled for now since we don't support CP14"
"config registers and jumping to ThumbEE vectors\n");
return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
case MISCREG_ID_PFR1:
warn("reading unimplmented register ID_PFR1");
return 0;
case MISCREG_ID_MMFR0:
return 0x03; //VMSAz7
case MISCREG_CTR:
@ -219,7 +213,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
case MISCREG_PMCR:
case MISCREG_PMCCNTR:
case MISCREG_PMSELR:
warn("Not doing anyhting for read to miscreg %s\n",
warn("Not doing anything for read to miscreg %s\n",
miscRegName[misc_reg]);
break;
case MISCREG_FPSCR_QC:

6
src/arch/arm/miscregs.hh
View file

@ -174,9 +174,9 @@ namespace ArmISA
MISCREG_CPSR_MODE,
MISCREG_LOCKFLAG,
MISCREG_LOCKADDR,
MISCREG_ID_PFR1,
MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_PFR1,
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
MISCREG_ID_MMFR1,
@ -236,10 +236,10 @@ namespace ArmISA
"pmceid1", "pmc_other", "pmxevcntr",
"pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"cpsr_mode", "lockflag", "lockaddr",
"cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
// Unimplemented below
"tcmtr",
"id_pfr1", "id_dfr0", "id_afr0",
"id_dfr0", "id_afr0",
"id_mmfr1", "id_mmfr2",
"aidr", "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",

7
src/arch/arm/system.cc
View file

@ -104,6 +104,13 @@ ArmSystem::initState()
// Set the initial PC to be at start of the kernel code
threadContexts[0]->pcState(kernelEntry & loadAddrMask);
}
for (int i = 0; i < threadContexts.size(); i++) {
if (params()->midr_regval) {
threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
params()->midr_regval);
}
}
}
ArmSystem::~ArmSystem()

5
src/arch/arm/tlb.hh
View file

@ -236,6 +236,11 @@ protected:
miscRegValid = true;
}
public:
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
inline void invalidateMiscReg() { miscRegValid = false; }
};

9
src/dev/arm/RealView.py
View file

@ -75,7 +75,8 @@ class A9SCU(BasicPioDevice):
class RealViewCtrl(BasicPioDevice):
type = 'RealViewCtrl'
proc_id = Param.UInt32(0x0C000000, "Platform ID")
proc_id = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
class Gic(PioDevice):
type = 'Gic'
@ -145,7 +146,7 @@ class RealViewPBX(RealView):
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x4000000)
flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
@ -212,10 +213,12 @@ class RealViewEB(RealView):
kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
uart3_fake = AmbaFake(pio_addr=0x1000c000)
smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
smc_fake = AmbaFake(pio_addr=0x100e1000)
sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x10010000)
@ -261,4 +264,6 @@ class RealViewEB(RealView):
self.aaci_fake.pio = bus.port
self.mmc_fake.pio = bus.port
self.rtc_fake.pio = bus.port
self.flash_fake.pio = bus.port
self.smcreg_fake.pio = bus.port

9
src/dev/arm/rv_ctrl.cc
View file

@ -97,8 +97,12 @@ RealViewCtrl::read(PacketPtr pkt)
case Flags:
pkt->set<uint32_t>(flags);
break;
case IdReg:
pkt->set<uint32_t>(params()->idreg);
break;
default:
panic("Tried to read RealView I/O at offset %#x that doesn't exist\n", daddr);
warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
daddr);
break;
}
pkt->makeAtomicResponse();
@ -128,7 +132,8 @@ RealViewCtrl::write(PacketPtr pkt)
flags = pkt->get<uint32_t>();
break;
default:
panic("Tried to write RVIO at offset %#x that doesn't exist\n", daddr);
warn("Tried to write RVIO at offset %#x that doesn't exist\n",
daddr);
break;
}
pkt->makeAtomicResponse();