sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

O3: Fix an issue with a load & branch instruction and mem dep squashing

Browse source 
Instructions that load an address and are control instructions can
execute down the wrong path if they were predicted correctly and then
instructions following them are squashed. If an instruction is a
memory and control op use the predicted address for the next PC instead
of just advancing the PC. Without this change NPC is used for the next
instruction, but predPC is used to verify that the branch was successful
so the wrong path is silently executed.
This commit is contained in:
Geoffrey Blake 2011-05-13 17:27:00 -05:00
parent f7b3900c13
commit b79650ceaa
1 changed files with 10 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/cpu/o3/iew_impl.hh
View file

@ -485,8 +485,16 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
TheISA::PCState pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst);
TheISA::PCState pc;
if (inst->isMemRef() && inst->isIndirectCtrl()) {
// If an operation is a control operation as well as a memory
// reference we need to use the predicted PC, not the PC+N
// This instruction will verify misprediction based on predPC
pc = inst->readPredTarg();
} else {
pc = inst->pcState();
TheISA::advancePC(pc, inst->staticInst);
}
toCommit->pc[tid] = pc;
toCommit->mispredictInst[tid] = NULL;